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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 楊佳玲(Chia-Lin Yang) | |
dc.contributor.author | Shun-Chih Yu | en |
dc.contributor.author | 游舜志 | zh_TW |
dc.date.accessioned | 2021-06-16T05:20:18Z | - |
dc.date.available | 2014-09-15 | |
dc.date.copyright | 2014-08-25 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-15 | |
dc.identifier.citation | [1] Benjamin C Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger. Phase-change technology and the future of main memory. IEEE micro, 30(1):143, 2010.
[2] SimoneRaoux,GeoffreyWBurr,MatthewJBreitwisch,CharlesTRettner,Yi-Chou Chen, Robert M Shelby, Martin Salinga, Daniel Krebs, S-H Chen, Hsiang-Lan Lung, et al. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development, 52(4.5):465–479, 2008. [3] B.C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In ACM SIGARCH Computer Architecture News,volume 37, pages 2–13. ACM, 2009. [4] MoinuddinKQureshi,MicheleMFranceschini,andLuisAlfonsoLastras-Montaño. Improving read performance of phase change memories via write cancellation and write pausing. In High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, pages 1–11. IEEE, 2010. [5] Sangyeun Cho and Hyunjin Lee. Flip-n-write: a simple deterministic technique to improve pram write performance, energy and endurance. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 347–357. IEEE, 2009. [6] Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, and Zili Shao. Pcm-ftl: A write- activity-aware nand flash memory management scheme for pcm-based embedded systems. In Real-Time Systems Symposium (RTSS), 2011 IEEE 32nd, pages 357–366. IEEE, 2011. [7] Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H Loh, and Doug Burger. Preventing pcm banks from seizing too much power. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, pages 186–195. ACM, 2011. [8] Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Duckmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaehwan Kim, Yong-Jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, H. Horii, Jaewook Lee, Kisung Kim, Hansung Joo, Kwangjin Lee, Yeong-Taek Lee, Jeihwan Yoo, and G. Jeong. A 20nm 1.8v 8gb pram with 40mb/s program bandwidth. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pages 46 –48, feb. 2012. [9] Yu Du, Miao Zhou, Bruce R Childers, Daniel Mossé, and Rami Melhem. Bit mapping for balanced pcm cell programming. In Proceedings of the 40th Annual International Symposium on Computer Architecture, pages 428–439. ACM, 2013. [10] Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. Throughput enhancement for phase change memories. 2013. [11] Lei Jiang, Youtao Zhang, Bruce R Childers, and Jun Yang. Fpb: fine-grained power budgeting to improve write throughput of multi-level cell phase change memory. In Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pages 1–12. IEEE Computer Society, 2012. [12] Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, and Bruce R Childers. Improving write operations in mlc phase change memory. In High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pages 1–10. IEEE, 2012. [13] Kwang-jinLee,Choong-keunKwak,andDu-eungKim.Nonvolatilememorydevice and related methods of operation, March 6 2008. US Patent 20,080,056,023. [14] T Nirschl, JB Philipp, TD Happ, GW Burr, B Rajendran, MH Lee, A Schrott, M Yang, M Breitwisch, CF Chen, et al. Write strategies for 2 and 4-bit multi- level phase-change memory. In Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pages 461–464. IEEE, 2007. [15] A. Patel, F. Afram, Shunfei Chen, and K. Ghose. Marss: A full system simula- tor for multicore x86 cpus. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 1050 –1055, june 2011. [16] M.T. Yourst. Ptlsim: A cycle accurate full system x86-64 microarchitectural sim- ulator. In Performance Analysis of Systems Software, 2007. ISPASS 2007. IEEE International Symposium on, pages 23 –34, april 2007. [17] Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. Dramsim2: A cycle accurate memory system simulator. Computer Architecture Letters, 10(1):16–19, 2011. [18]JohnLHenning.Speccpu2006benchmarkdescriptions.ACMSIGARCHComputer Architecture News, 34(4):1–17, 2006. [19] Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. The parsec benchmark suite: Characterization and architectural implications. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pages 72–81. ACM, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56244 | - |
dc.description.abstract | 作為被看好的新一代記憶體之一,相變化記憶體 (Phase-Change- Memory) 擁有多項優於傳統隨機存取記憶體 (DRAM) 之優點,如較高 的單元密度 (cell density) 及零靜態功率 (leakage power) 等。除了寫入耗 損問題 (wear-out) 及較長的寫入延遲 (write latency) 外,相變化記憶體 也面臨了因高寫入功率所帶來的能源議題。先前研究指出相變化記憶 體之內部能源供應並無法支援同時對所有寫入請求之操作並提出能源 預算限制 (power budget limitation),而我們發現此現象隨著最底層快取 記憶體 (last-level cache) 的快取線 (cache line) 之增大變得更嚴重。雖然 區段寫入技術 (division programming) 是個可行的解決方案,其造成之 效能耗損仍相當可觀。
在這篇論文中,我們提出細粒度之寫入排程機制以增進相變化記憶 體於能源預算限制下之效能。我們發現區段寫入技術主要有兩項缺點: 其一,所有屬於同一寫入請求之區段必須被共同地排程,意味著對無 法被發出 (un-issuable) 的區段之搶先 (preemption) 是不可行的而損害效 能。其二,將寫入請求分割為區段之方法為靜態地依照位元位置 (bit position),其喪失了動態調整各區段能源消耗之彈性。根據此觀察,我 們提出了兩個方法。首先,次請求排程 (sub-request scheduling) 使排程 器 (scheduelr) 可進行區段粒度之排程以支援對無法寫入區段之搶先。 第二,動態區段分割 (dynamic division) 可於運行時藉由搬移欲寫入之 資料以調整各區段間之能源配置 (power allocation)。我們的實驗結果展 示了這些機制能有效地增進系統效能達 31%。 | zh_TW |
dc.description.abstract | As a promising candidate for future memory, Phase-Change-Memory (PCM) has several advantages over traditional DRAM, such as high cell density and zero leakage power. In addition to the wear-out problem and longer write latency, PCM also faces power issue with high write power. Prior works ad- dress the power budget limitation that the internal power supply could not sustain programming all the write requests for all banks simultaneously, and we find that this situation even gets worse with enlarged last-level cache line. Though division programming technique is a possible solution, the perfor- mance degradation is still substantial.
In this thesis, we propose fine-grained write scheduling to improve the performance of Phase-Change-Memory under power budget limitation. There are two major problems with division programming of PCM write operation: (1) all the divisions of a write request are scheduled collectively, indicating that the preemption of un-issuable divisions is unfeasible and degrades the performance; (2) divisions are divided statically by bit positions, which is lack of flexibility to manage the power consumption of each divisions at runtime. Based on these observations, we propose two schemes. First, sub-request scheduling enables scheduler to schedule under the granularity of divisions to support the preemption of un-issuable write divisions. Second, dynamic division adjusts the power allocation of each division by shifting the data to be written at runtime. Our experimental results show that these techniques improve the system performance significantly by up to 31%. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T05:20:18Z (GMT). No. of bitstreams: 1 ntu-103-R01922008-1.pdf: 923215 bytes, checksum: ee1a5033fd69d4b77450d81ae60b5716 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 致謝 i 摘要 ii Abstract iv
1 Introduction 1 2 Background and Related Works 4 3 Sub-request Scheduling 9 4 Dynamic Division 12 5 Experimental Evaluation 15 5.0.1 ConfigurationsandMethodology ................. 15 5.0.2 PerformanceImprovement..................... 17 5.0.3 QueueSize ............................. 20 6 Conclusion 21 Bibliography 22 | |
dc.language.iso | en | |
dc.title | 以細粒度之寫入排程機制增進相變化記憶體於能源預 算限制下之效能 | zh_TW |
dc.title | Fine-grained Write Scheduling to Improve PCM Performance under Power Budget Limitation | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂士濂(Shih-Lien Lu),徐慰中(Wei-Chung Hsu),洪士灝(Shih-Hao Hung) | |
dc.subject.keyword | 相變化記憶體,記憶體排程,能源預算,區段寫入, | zh_TW |
dc.subject.keyword | Phase-Change-Memory,Memory Scheduling,Power Budget,Division Programming, | en |
dc.relation.page | 24 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-08-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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