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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Yi-Chu Chen | en |
dc.contributor.author | 陳奕竹 | zh_TW |
dc.date.accessioned | 2021-06-16T05:17:41Z | - |
dc.date.available | 2014-08-26 | |
dc.date.copyright | 2014-08-26 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-17 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56171 | - |
dc.description.abstract | 隨著無線通訊系統的發展,頻譜使用效率與功率效率為主要的設計考量。本論文提出了一個採用D-1型功率放大器與變壓器型功率結合器所實現之相位反調發射器。現有的發射器因為振幅調變路徑限制,功率效率低落。反相位發射器將低效率的振振幅調變路徑移除,僅留下固定振幅的相位調變信號,因此高效率的非線性功率放大器可以被使用。本作品中,利用低功率消耗的相位選擇器來實現相位調變器。在晶片中的變壓器除了當功率放大器的匹配網路外,也扮演了功率結合器的角色,如此一來,一個完整的相位反調無線發射器可以整合至單晶片中。
本作品為一應用於二十四億赫茲之無線發射器,可支援4-QAM、16-QAM與64-QAM之調變。本晶片實現於90奈米金氧半導體製程。實驗結果顯示在輸出功率20 dBm 下的傳輸速度為48Mbps。其錯誤向量值為在64-QAM調變之下小於12%。在操作電壓1.2伏特下之功率消耗為360毫瓦。 | zh_TW |
dc.description.abstract | For the next generation wireless communication, spectral efficiency and power efficiency are main design considerations. The thesis presents a fully integrated outphasing transmitter with inverse Class-D (D-1) power amplifier and transformer-based power combiner. Existing transmitters suffer from low efficiency due to amplitude modulation (AM) path. Utilizing the outphasing technique, the AM path is eliminated. Due to only constant-envelope phase modulation, the non-linear switching power amplifier can be adopted to obtain high power efficiency. In this work, low power phase selector is used in the modulator to realize an efficient phase modulator. On-chip transformer acts as a matching network of power amplifier and power combiner. In this way, area can be reduced. Hence, the outphasing transmitter is integrated fully.
This work presents a 2.4-GHz wireless transmitter which can support 4-QAM, 16-QAM, and 64-QAM. The chip is fabricated in TSMC 90-nm CMOS process. The experiments results show that transmitter deliver 48-Mbps data rate with output power 20 dBm. The EVM of 64-QAM modulation is lower than 12 % and the total power consumption 360mW under a 1.2-V supply voltage. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T05:17:41Z (GMT). No. of bitstreams: 1 ntu-103-R00943115-1.pdf: 3136748 bytes, checksum: 38d07e46fdeaf665892a4443917372b9 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 口試委員會審定書 iii
摘要 ix ABSTRACT xi Table of Contents xiii LIST OF FIGURES xvi LIST OF TABLES xx Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Overview 6 Chapter 2 Transmitter Architecture & Outphasing Operation 7 2.1 Introduction 7 2.2 Transmitter Architecture for a Variable-Envelope Signal 7 2.2.1 Cartesian (I/Q) Transmitter 8 2.2.2 Polar Transmitter 9 2.2.3 Outphasing Transmitter 11 2.3 Background of Outphasing Technique Transmitter 11 2.3.1 Operation of Outphasing Transmitter 12 2.3.2 Mathematic Description of Outphasing Operation 13 2.4 Prior Works of Outphasing Transmitter 15 2.4.1 Digital Phase Rotator-based Outphasing Modulator 15 2.4.2 Delay-based Wideband Outphasing Modulator 17 2.4.3 Digital Phase Modulator 18 2.4.4 Digital Delay Line-based Outphasing Modulator 18 2.5 Design of Power Combiner 19 2.5.1 Phase Resolution 19 2.5.2 Design of Power Combiner 19 2.6 Summary 20 Chapter 3 Proposed Outphasing Transmitter 21 3.1 Transmitter Architecture 21 3.2 System Requirement 21 3.3 Key Building Blocks 23 3.3.1 Phase Modulator 23 3.3.2 Non-Linear Switching Power Amplifier 26 3.3.3 On-Chip Transformer 30 3.3.4 Transformer-based Power Combiner 32 3.4 Circuits Implementation 34 3.4.1 Multi-Phase Generator 34 3.4.2 Error Averaging Circuits 37 3.4.3 Phase Interpolation Circuit 39 3.4.4 Digitally-Controlled Delay Line (DCDL) 39 3.4.5 Power Amplifier and Power Combiner 40 3.5 Simulation Results 45 3.5.1 Multi-Phase Generator 45 3.5.2 Some Blocks of Phase Modulator 47 3.5.3 On-Chip Transformer 48 3.5.4 Power Amplifier and Power Combiner 49 Chapter 4 Experimental Results 51 4.1 Chip Photo 51 4.2 The Voltage Regulator with High Output DC Current 51 4.3 Experimental Results 52 4.3.1 D -1 PA measurements 52 4.3.2 Outphasing Transmitter Measurements 53 4.3.3 Analysis 55 4.3.4 Overhead Summary 56 4.4 Summary of Experimental Results 57 Chapter 5 Conclusion and Future Work 59 5.1 Conclusions 59 5.2 Future Work 59 References 61 | |
dc.language.iso | en | |
dc.title | 使用D-1型功率放大器與變壓器型功率結合器之相位反調無線發射器 | zh_TW |
dc.title | A Fully Integrated Outphasing Transmitter with Inverse Class-D (D-1) Power Amplifier and Transformer-based Power Combiner | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林永裕(Yung-Yu Lin),曾英哲(Ying-Che Tseng) | |
dc.subject.keyword | 相位反調,變壓器型功率結合器,D-1功率放大器, | zh_TW |
dc.subject.keyword | Outphasing,Transformer-based power combiner,Class-D-1 power amplifier, | en |
dc.relation.page | 66 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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