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標題: | 利用遠程電漿輔助原子層沉積技術製作摻雜氮之結晶化高介電常數金屬閘極堆疊之研究 Study of Nitrogen-doped Crystalline High-K/Metal Gate Stacks Prepared by Remote Plasma Atomic Layer Deposition |
作者: | Jhih-Jie Huang 黃芝傑 |
指導教授: | 陳敏璋(Miin-Jang Chen) |
關鍵字: | 高介電係數介電層,二氧化鋯,原位原子層摻雜,沉積後氮化處理,緩衝層,遠程電漿輔助原子層沉積技術, high-K gate dielectrics,zirconium oxide,in-situ atomic layer doping,post-deposition nitridation,buffer layer,remote plasma atomic layer deposition, |
出版年 : | 2014 |
學位: | 博士 |
摘要: | 本論文研究利用遠程電漿輔助型原子層沉積技術(RP-ALD)製備高介電係數(High-K)材料二氧化鋯(ZrO2)薄膜於矽基板上,並將其製作成金屬/絕緣層/半導體(MIS)之電容元件結構,探討其材料性質與相關之電性。
論文中,第一部分主要討論氮化處理(nitridation)對於結晶化之二氧化鋯薄膜的效應。透過原位原子層摻雜技術(in-situ atomic layer doping),分別使用不同氮源(氮氣及氨氣)將氮元素摻雜至二氧化鋯氧化層內,實驗結果發現,含氮之二氧化鋯薄膜應用於金氧半電容元件中,等效電容厚度(capacitance equivalent thickness CET)、漏電流及應力所致的漏電流(stress-induced leakage current SILC)有顯著下降,此外,相較於使用氮氣作為氮源,由於氨氣解離出之氫原子對於界面缺陷可產生鈍化反應,同時明顯降低界面缺陷的密度(interfacial state density)。緊接著,文章討論利用相同氮源(氨氣)但不同氮化的方式-原位原子層摻雜及沉積後氮化處理(post-deposition nitridation)-對於二氧化鋯薄膜的影響,透過氮元素縱深分析,兩種不同摻雜方式造成在氧化層中氮元素不同的分布,由於沉積後氮化處理摻雜的氮元素主要集中在氧化層靠近金屬界面處,能有效阻擋氧擴散至矽基板,因而抑制界面層(interfacial layer IL)的生長,成功製作出低等效電容厚度1.13 nm及低漏電流密度1.35×10-5 A/cm2的金氧半電容元件。上述結果證實,氮元素在氧化層中的分布對於金氧半電容元件的電性有顯著的影響。 另一個部分討論雙層結構(二氧化鋯及矽基板之間放入高能隙、熱穩定高之二氧化鋁(Al2O3)薄膜)應用於金氧半電容閘極層的效應。由於緩衝層(buffer layer)氧化鋁具有高能隙,加上基於之前氮化處理的經驗將其氮化處理後,由結晶化二氧化鋯/氮化處理之氧化鋁所構成的疊層閘極層將等效電容值降低至1.2 nm、漏電流密度降至8.12×10-6 A/cm2且界面缺陷密度也降至2.77×1011 cm-2eV-1。此外,透過光激發螢光(photoluminescence PL)的強度變化,可以提供快速定性檢測矽基板和氧化層之間的介面缺陷密度。最後,分別利用氮氣及氨氣作為氮源將結晶化二氧化鋯及緩衝層二氧化鋁做氮化處理,透過二次氮化處理(double nitridation)及雙層結構,等效電容值厚度可降低至1.09 nm,同時漏電流可維持在3.43×10-5 A/cm2,此外,遲滯現象也由於熱穩定性的提升,經由退火至800 oC後,獲得明顯下降仍維持相同電容值厚度,實驗結果顯示二次氮化處理後之-結晶化高介電係數氧化層/緩衝層-閘極疊層未來將可應用於次奈米(sub-nanometer)之金氧半電容元件。 High-K dielectric zirconium oxide (ZrO2) was fabricated by the Remote Plasma Atomic Layer Deposition (RP-ALD) technique. In this thesis, the first part discusses the effect of nitridation on ZrO2 gate dielectrics. The crystalline ZrO2 high-K gate dielectrics treated with in-situ atomic layer doping of nitrogen using remote N2 and NH3 plasma were investigated, to suppress the capacitance equivalent thickness (CET), and leakage current density (Jg). The stress-induced leakage current (SILC) was reduced significantly as well. In addition, the interfacial states density (Dit) was also reduced by hydrogen passivation as a result of the remote NH3 plasma treatment. Next, the electrical characteristics of crystalline ZrO2 gate dielectrics with different nitrogen depth profiles were investigated, which were treated by the in-situ atomic layer doping of nitrogen and post-deposition nitridation processes, respectively, using remote NH3 plasma at a low treatment temperature of 250 oC. As compared with the in-situ atomic layer doping of nitrogen, the post-deposition nitrogen process leads to a lower capacitance equivalent thickness of 1.13 nm with a low leakage current density of 1.35×10-5 A/cm2. The enhanced capacitance density caused by the post-deposition nitrogen treatment was ascribed to the high nitrogen concentration at the top surface of gate dielectric, giving rise to the suppression of oxygen diffusion toward the interface and so a thinner interfacial layer. The result reveals that the nitrogen depth profile has significant impact on the electrical properties of the gate dielectrics in the advanced metal-oxide-semiconductor devices. The other part discusses the effect of the bilayer structure based on the combination of ZrO2 and buffer layer Al2O3. The gate stack composed of crystalline ZrO2 high-K dielectrics and nitrided Al2O3 buffer layer was investigated to reduce the CET, Jg, and Dit. The Jg was suppressed by the insertion of the Al2O3 buffer layer between ZrO2 and Si. A suppressed Jg of 8.12×10-6 A/cm2 and Dit of 2.77×1011 cm-2eV-1 were achieved in the crystalline ZrO2/nitrided Al2O3 gate stack with a low CET of 1.2 nm. The gate stack was also optically probed through the photoluminescence from Si, revealing that the hydrogen passivation and depassivation effects caused by the remote NH3 plasma treatment are highly correlated with the Dit. Finally, the gate dielectric stack composed of crystalline ZrO2 and Al2O3 buffer layer treated with double nitridation was developed to reduce the CET, Jg, Dit, and enhance thermal stability as well. The Jg and Dit were suppressed by the insertion of the Al2O3 buffer layer treated with remote NH3 plasma nitridation. A further nitridation using remote N2 plasma on ZrO2 was carried out to reduce the CET and Jg. Accordingly, a low CET of 1.09 nm, Jg of 3.43×10-5 A/cm2, and Dit of 3.35×1011 cm-2eV-1 were achieved in the crystalline ZrO2/Al2O3 buffer gate stack treated with the double nitridation. The hysteresis was also minimized significantly by the post-deposition annealing at 800 oC, which is attributed to the enhanced thermal stability. The results indicate that the crystalline high-K dielectrics/buffer layer with double nitridation treatments is a promising gate stack structure beneficial to the sub-nanometer CET scaling in the future. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55755 |
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顯示於系所單位: | 材料科學與工程學系 |
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