利用多位準快閃記憶體之寫入異質性改善尖峰 I/O 效能

Abstract

隨著快閃記憶體的單位儲存成本持續下跌，企業開始廣泛選用基於多位準快閃記憶體的固態硬碟作為其儲存系統。然而，由於快閃記憶體先天在讀取與寫入速度上的不對稱，寫入速度經常成為儲存系統的效能瓶頸。又因為伺服器環境有許多 I/O 工作是瞬間爆量的，在尖峰負載時必須處理的寫入請求數目有可能比平時還要高出一個數量級甚至更多，這使得企業必須極大程度地超額配置其儲存系統，以確保在尖峰負載下的寫入延遲時間依能滿足企業內部對於儲存系統的服務層級目標，例如 99 百分位數的 I/O 延遲時間必須少於 100 毫秒。 多位準快閃記憶體的寫入異質性（多位準/單位準模式寫入）有很大的機會能改善尖峰寫入延遲時間，使企業可以用較少的超額配置成本讓儲存系統達成原本服務層級目標的延遲時間要求。然而，為了盡可能減輕因為單位準模式寫入而造成的壽命減損，我們在本論文當中提出了一個服務層級目標感知的固態硬碟架構，能夠只使用極少的單位準模式寫入就達成服務層級目標。我們提出的固態硬碟架構包含了一個嶄新的演算法，它能夠同時排程每個寫入請求的執行順序以及寫入模式。我們的排程演算法能夠迅速找到一個局部最佳排程，使得在不考慮未來可能出現的讀寫請求的前提下，對於目前已出現的每一個寫入請求都能滿足我們所指定的延遲時間目標（例如 100 毫秒），而所使用的單位準模式寫入數目卻是最少的。除非任何排程都沒辦法滿足我們所指定的延遲時間目標，否則我們的演算法一定可以找到一個局部最佳排程。另一方面，為了要避免固態硬碟由於未來出現的讀寫爆量而違反服務層級目標，我們提出的固態硬碟架構會在原本服務層級目標所指定的延遲時間目標（例如 100 毫秒）內，適應性地加入一些安全邊界（例如 15 毫秒），使得實際作用於排程演算法的是一個較短的延遲時間目標（例如 85 毫秒），這會讓許多寫入請求提早被做完，空出時間讓固態硬碟得以容忍更多未來出現的讀寫請求。 就我們所知，本論文是第一篇探討以多位準快閃記憶體的寫入異質性來達成服務層級目標的研究。實驗結果顯示，基於我們提出的服務層級目標感知的固態硬碟架構，儲存系統可能在完全不需要超額配置更多儲存節點的情形下就滿足服務層級目標。我們改善了 99 百分位數的 I/O 延遲時間高達 16 倍，但從固態硬碟的總擦除次數來看，我們只造成 2.9% 的壽命減損。

The ever-growing capacity and continuously-dropping price have enabled the MLC SSDs to be widely adopted in the enterprises' storage subsystems. However, due to the NAND Flash's asymmetric read/write latency, the write performance is often the I/O bottleneck of the MLC SSD-based storage subsystems. Moreover, since many server I/O workloads are bursty, the storage subsystems may experience peak write request rates that are over an order of magnitude higher than average load. This requires significant overprovisioning for peaks in order to make the peak write latency meet the enterprises' internal SLOs (Service-Level Objectives) for their storage subsystems, such as the 99th percentile I/O latency < 100ms. The write heterogeneity (i.e. the MLC/SLC-mode write) in MLC SSDs provides great potential for the storage subsystems to improve the peak write latency, reducing the cost of massive overprovisioning for meeting the SLO's latency requirement. To minimize the lifetime impact of the SLC-mode writes, in this thesis, we propose a SLO-aware SSD Architecture which meets the SLO with minimal SLC-mode writes used. This architecture includes a novel algorithm to schedule both the issuing sequence and the SLC/MLC mode of each write request. Our scheduling algorithm can quickly find a local optimal schedule such that if there's no read and write requests in the future, all the write requests which have arrived in the SSD can meet the given targeted latency (e.g. 100ms) with minimal SLC-mode writes used. Unless there's no schedule which can meet the given targeted latency, our scheduling algorithm can always find this local optimum. To prevent the SSD from violating the SLO due to the read or write bursts in the future, this architecture adaptively adds a safety margin (e.g. 15ms) to the SLO's targeted latency value (e.g. 100ms), resulting in a smaller targeted latency value (e.g. 85ms) actually used for the scheduling algorithm. This makes the requests finish earlier, enabling the SSD to tolerate more read or write bursts in the future. To our knowledge, this is the first work targeted for the SLO by exploiting the write heterogeneity of the MLC NAND Flash. The experimental results show that with the help of our SLO-aware SSD Architecture, it's possible to meet the SLO without the need of overprovisioning more storage nodes. The 99th percentile I/O latency is significantly improved by up to 16x with only 2.9% lifetime impact in terms of the total erase count.