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標題: | 基於環狀輪廓考慮障礙物之巨集電路擺置 Circular-Contour-Based Blockage-Aware Macro Placement |
作者: | Chien-Hsiung Chiou 邱建雄 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 實體設計,電路擺置,可繞度,巨集電路,超大型積體電路設計, Physical Design,Placement,Routability,Macro,VLSI Design, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 由於廣泛地使用矽智財(Intellectual Property)巨集電路,一個現代化的系統單晶片(System-on-a-Chip)通常包含有一定數量的巨集電路。有一些巨集電路因為各種因素,例如功耗以及針角的位置,需要以特定的方向放置在規定的位置,稱之為預先擺置巨集電路。現代的系統單晶片存在著預先擺置巨集電路以及大型巨集電路加深了混合尺寸電路擺置問題的複雜度。現有的文獻中提出的方法可能無法對現代的混合尺寸設計提供合理的擺置。因此在這篇論文中,我們提出了一個三階段的混合尺寸佈局流程,其中包括:(1)擺置原型,(2)巨集電路擺置,和(3)標準單元擺置。巨集電路擺置在整個混合尺寸擺置器中扮演一個關鍵的角色,因此我們專注在這個問題上。我們所提出的巨集電路擺置器同時優化了線長,可繞度,以及標準單元佈局區域。首先,我們提出了環狀輪廓資料結構,它能有效地描述所有預先擺置巨集電路。基於這個資料結構,我們可以有效地避免巨集電路之間發生重疊。同時也可以優化標準單元佈局區域的形狀和面積。不同於以往的巨集電路擺置器,其往往花費太大的計算時間尋找可行的解,我們提出的環狀堆機方案,將可移動的巨集電路安放在環狀輪廓周邊,可以有效地產生可行解,並協助模擬退火(Simulated Annealing)專注於優化解的質量。實驗結果證實,我們所提出的演算法能夠比業界的人工手動擺置巨集電路以及學術界最先進的混合尺寸擺置器得到更好的結果。 Due to the wide use of intellectual property (IP) macros, a modern system-on-a-chip (SoC) usually contains a significant number of large macros. Some macros, namely pre-placed macros, need to be placed at specified positions and in certain orientations due to various considerations, such as power and pin locations. The existence of pre-placed macros and large macros in modern SoCs has complicated modern mixed-size placement. However, existing works may fail to obtain a legal placement for modern mixed-size designs. Therefore, in this thesis, we present a three-stage mixed-size placement flow, which consists of: (1) placement prototyping, (2) macro placement, and (3) standard-cell placement. We focus on the macro placement stage, which plays a key role to determine the mixed-size placement quality. The proposed macro placer simultaneously optimizes wirelength, routability, and standard-cell placement region. We first propose a circular contour that can model all of the pre-placed macros. Based on the proposed circular contour, we can effectively avoid the overlap between movable macros and pre-placed macros. Meanwhile, the shape and area of the standard-cell placement region can also be optimized. Unlike previous macro placers that often spend much computational effort on searching a feasible solution, our circular packing scheme, which packs movable macros around the circular contour, can generate feasible solutions efficiently, and assist simulated annealing (SA) to focus on the optimization of solution quality. Experimental results show that our algorithm can achieve the best quality among both manual macro placements provided by industry and the leading academic mixed-size placers on industrial benchmarks. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55399 |
全文授權: | 有償授權 |
顯示於系所單位: | 電機工程學系 |
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