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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Jung-Hong Po | en |
dc.contributor.author | 薄榮鴻 | zh_TW |
dc.date.accessioned | 2021-06-16T03:54:33Z | - |
dc.date.available | 2015-02-04 | |
dc.date.copyright | 2015-02-04 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-12-29 | |
dc.identifier.citation | [1] J. C. Moreira and P. G. Farrell, Essentials of Error-Control Coding, Wiley, pp. 277-324, 2006.
[2] E. Arikan, “Channel Combining and Splitting for Cutoff Rate Improvement,” IEEE Transactions on Information Theory, vol. 52, no.2, pp. 628-639, Feb. 2006. [3] E. Sasoglu, E. Telatar, and E. Arikan, “Polarization for Arbitrary Discrete Memoryless Channels,” IEEE Information Theory Workshop, pp. 144-148, Oct. 2009. [4] P. Shi, W. Tang, S. Zhao, and B. Wang, “Performance of Polar Codes on Wireless Communication Channels,” IEEE 14th International Conference on Communication Technology, pp. 1134-1138, Apr. 2012. [5] E. Arikan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-input Memoryless Channels,” IEEE Transactions on Information Theory, vol. 55, no 7, pp. 3051-3073, July 2009. [6] C. Zhang, K.K. Parhi, “Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder,” IEEE Transactions on Signal Processing, vol.61, no.10, pp.2429-2441, May. 2014. [7] A. Eslami and H. Pishro-Nik, “A Practical Approach to Polar Codes,” IEEE International Symposium on Information Theory Proceedings, pp. 16-20, July 2011. [8] E. Arikan and E. Telatar, “On the Rate of Channel Polarization,” IEEE International Symposium on Information Theory, pp. 1493-1495, July 2009. [9] I. Tal and A. Vardy, “How to Construct Polar Codes,” IEEE Transactions on Information Theory, vol. 59, no. 10, pp. 6562-6582, Oct. 2013. [10] I. Tal and A. Vardy, “List Decoding of Polar Codes,” IEEE International Symposium on Information Theory, pp. 1-5, July 2011. [11] R. Mori and T. Tanaka, “Performance and Construction of Polar Codes on Symmetric Binary-Input Memoryless Channels,” IEEE International Symposium on Information Theory, pp. 1496–1500, July 2009. [12] C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, “A Semi-Parallel Successive-Cancellation Decoder for Polar Codes,” IEEE Transactions on Signal Processing, vol. 61, no. 2, pp. 289-299, Jan. 2013. [13] C. Leroux, I. Tal, A. Vardy, and W. J. Gross, “Hardware Architectures For Successive Cancellation Decoding of Polar Codes”, IEEE International Conference on Acoustics, Speech and Signal Processing , pp. 1665-1668, May 2011. [14] A. Pamuk, “An FPGA Implementation Architecture for Decoding of Polar Codes,” IEEE International Symposium on Wireless Communication Systems, pp. 437-441, Nov. 2011. [15] G. Berhault, C. Leroux, C. Jego, and D. Dallet, “Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes,” IEEE Workshop on Signal Processing Systems, pp. 407-412, Oct. 2013. [16] U. U. Fayyaz and J. R. Barry, “Low-Complexity Soft-Output Decoding of Polar Codes,” IEEE Journal on Selected Areas in Communications, vol.32, no.5, pp. 958-966, May 2014. [17] N. Hussami, S. B. Korada, and R. Urbanke, “Performance of Polar Codes for Channel and Source Coding,” IEEE International Symposium on Information Theory, pp. 1488-1492, July, 2009. [18] A. Mishra, A. J. Raymond, L. G. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, and W. J. Gross, “A successive Cancellation Decoder ASIC for a 1024-bit Polar Code in 180nm CMOS,” IEEE Asian Solid-State Circuits Conference, pp. 205-208, Nov. 2012. [19] B. Xiang, D. Bao, S. Huang, and X. Y. Zeng, “An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1416-1432, June 2011. [20] C. Zhang, Bo Yuan, and K. K. Parhi, “Reduced-Latency SC Polar Decoder Architectures,” IEEE International Conference on Communications, pp. 3471-3475, June 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55279 | - |
dc.description.abstract | 通道編碼的概念是利用增加多餘的訊息,讓訊息在傳輸時能夠達到更佳的正確性,以消除通道傳輸過程中的雜訊。許多專家學者都致力於研究此系統,期望可以建構出一套在傳輸速率小於通道容量的條件下,可以有效傳送訊息的編碼系統。極性編碼(Polar Codes) 運用了通道分解將不同的通道容量算出來,並且使用巴氏參數,來計算出固定增加點,再使用接續取消解碼(Successive Cancellation Decoding)的方式下,理論上可以達到上述的需求。
在接續消除解碼的架構上,需要連續的解碼資料,即需要將前面解碼後的結果,然後繼續解碼下面的資料,這是一個相當沒有效率的解碼方式。因此我本文提之解碼的處理器之目標為降低對於接續消除解碼前面資訊的需求,並且將極性編碼迭代時所擁有的累積效果延續,希望可以將同一套硬體架構可以處理多種碼長,並且藉由修正處理單元(Processing Element)以達到提高解碼效率的硬體架構。最近的文章有使用軟數值(Soft Value)來當作計算的數值,這在模擬表現上能夠優於原始的狀況但是並沒有對其硬體產生出相對應的架構,但如結合我們所提供的想法在此架構上,可以有效建立出一個可實踐此方法的硬體架構,這是本論文的另一個主要研究內容。 在本篇論文中,我們使用了接續消除解碼的解碼演算法,在硬體架構上把解碼的架構做排程與規劃上做了更動,藉由單一的解碼架構,做出多種碼長都可處理的排程規劃。此外我們也提出了一個可以有效將軟數值解碼的極性編碼解碼器架構。我們實踐了一個架構可以減少1/4的時脈數目,並且可以解碼不同的碼長256,512不同碼率0.5以及0.75的架構,我們這樣的架構充分運用極性編碼的可變動性,實踐出一個可以應用於不同狀況時的解碼方式。 | zh_TW |
dc.description.abstract | Channel coding is a technique which adds redundancy to the messages in order to increase the reliability of transmission. Many works have been devoting to construct a coding scheme that can transmit messages reliably at rates set below the channel capacity. Polar code is one such scheme that can achieve channel capacity theoretically under successive cancellation (SC) decoding.
SC decoder needs to process data serially. New data generation needs to process previous information. Therefore, we can find that this decoder is a very inefficient structure. In this work, we proposed a processing element (PE) to solve the SC decoding problem. And we want to use the SC decoder symmetric structure to implement a hardware which can process information with different code lengths. Besides, there is an algorithm which uses the soft values to generate the partial sum information, which has a better performance. We also proposed a hardware structure to implement this algorithm efficiently, by modifying our SC PE. Our goal is to implement an SC polar code decoder to process multiple code-length data. We use a modified PE to increase the SC polar decoder throughput. Our proposed polar code SC decoder has a higher through-put channel code structure and a multi-code word structure. Moreover, we proposed a soft-output output polar decoding structure to improve the decoder performance. And this decoder can process data and save 1/4 clock cycles. The code lengths can be 512 and 256 bits and code rate can be 0.5 and 0.75. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T03:54:33Z (GMT). No. of bitstreams: 1 ntu-103-R01943044-1.pdf: 2385102 bytes, checksum: 31e720036400500037b010a5cdf2d7bf (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | ABSTRACT i
TABLE OF CONTENTS iii LIST OF FIGURES vii LIST OF TABLES ix CHAPTER 1 INTRODUCTION 1 1.1 Overview of Digital Communication System 1 1.2 Overview of Channel Coding 2 1.3 Multiple Code-Length Successive Cancellation (SC) Decoder 2 1.4 Thesis Organization 3 CHAPTER 2 CHANNEL POLARIZATION AND CAPACITY-ACHIEVING CODES 5 2.1 AWGN Channel 6 2.2 Channel Polarization 7 2.3 Polar Coding 7 2.4 Polar Code Construction 12 2.5 Channel Combining 13 2.6 Channel Splitting 14 2.7 Recursive Channel Transformations 15 2.8 Successive Cancellation Decoder Algorithm 17 2.8.1 SC Decoder Algorithm Steps 18 2.8.2 Min-Sum SC Decoding Algorithm 21 CHAPTER 3 ARCHITECTURE OF POLAR CODE DECODER 25 3.1 Fully-parallel Architecture 25 3.2 Tree Architecture 27 3.3 Line SC Architecture 28 3.4 Utilization Rate 30 3.5 Semi-Parallel Successive-Cancellation Decoder Architecture 31 3.6 Processing Element 35 CHAPTER 4 IMPLEMENTATION OF POLAR CODE DECODER 37 4.1 Formulas of SC decoder 37 4.2 SC Decoder Architecture 38 4.2.1 LLR Registers 39 4.2.2 Channel Buffer 40 4.2.3 Bypass Buffer 40 4.2.4 Partial Sum Registers 40 4.2.5 Partial Sum Update Logic 42 4.2.6 Controller 43 4.2.7 Processing Element 45 4.2.8 Code Length Rate Controller 47 4.2.9 Hard Decision Logic 48 4.3 Processing Element with Last Two States Combined 49 4.4 Introduction of Soft-Output Decoding of Polar Codes 51 4.5 Architecture for Soft-Output Decoding of Polar Codes 52 4.5.1 Soft-Output Polar Decoding Controller 53 4.5.2 Soft-Output Polar Decoding Partial Sum Registers 55 4.5.3 Soft-Output Polar Decoding Processing Element 56 4.5.4 Soft-Output Polar Decoding Final Stage Processing Element 57 CHAPTER 5 EXPERIMENTAL RESULTS 61 5.1 Design and Implementation Flow 61 5.2 Polar Code Simulation 62 5.2.1 Capacity and Bhattacharyya Parameters 62 5.2.2 SC Polar Code Performance 63 5.2.3 Soft-Output Polar Code Performance 65 5.3 Implementation Results 65 5.4 Comparison 66 CHAPTER 6 CONCLUSION 69 REFERENCE 71 | |
dc.language.iso | en | |
dc.title | 可變碼長的極性解碼器硬體設計與實現 | zh_TW |
dc.title | Implementation of a Multiple Code-Length Polar Code Decoder Architecture | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張錫嘉(Hsie-Chia Chang),游竹(Chu Yu),吳安宇(An-Yeu Wu) | |
dc.subject.keyword | 通道分解,對稱容量,巴氏參數,固定增加點, | zh_TW |
dc.subject.keyword | Symmetric Capacity,Bhattacharyya Parameters,Frozen Bits, | en |
dc.relation.page | 73 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-12-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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