高速單通道與多通道連續漸進式類比至數位轉換器

Abstract

在高速類比數位轉換器研究中，提出了一個八位元每秒七億次取樣的連續漸進式類比至數位轉換器與一個七位元每秒二十四億次取樣的免校正時間交錯式的類比至數位轉換器被提出，皆是以40奈米CMOS設計。 在第一個設計中，為了避免比較器陷入亞穩態的狀況，採用了一個延遲轉移技術，把比較器的延遲轉換成類似於管線式類比數位轉換器裡的一點五位元的保護區間，並且加速了解析速度。這顆晶片在每秒7億次的轉換之下，功率消耗為5mW。在奈奎斯特的輸入頻率下有七位元的有效位元，其FoM為56 fJ/c.-s.。因為沒有使用額外的校正電路，此晶片的面積只有0.006mm2。 在第二個設計中，為了解決偏移電壓不匹配的問題，採用了一個偏移電壓補償演算法，把通到間偏移電壓的不匹配轉換成非線性度，再透過創造保護區間去補償。因此此時間交錯式的類比數位轉換器無須校正，在每秒二十四億次的轉換之下，功率消耗為14mW。在低頻輸入時FoM為130 fJ/c.-s.。

In the field of high-speed ADC, an 8-bit 700MS/s single-channel SAR and 7-bit 2.4GS/s calibration-free time-interleaved ADC in 40nm CMOS are presented. In the first design, in order to skip the comparator metastability, a delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range which is similar to pipelined ADC, and it also accelerates the comparison speed. This SAR ADC in 40nm CMOS technology achieves an ENOB of 7 in Nyquist and consumes 5mW. It results in a FoM of 56fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.006mm2. In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it, so no calibration is required. This time-interleaved ADC in 40nm CMOS technology achieves an ENOB of 5.4 with low-frequency input and consumes 14mW. It results in a FoM of 130fJ/conversion-step.