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標題: | 基於估算負載變化量技術的同步全數位低壓差線性穩壓器 Synchronous Fully-Digital Low-Dropout Regulator Based on Load Current Change Estimation Technique |
作者: | Cheng-Chieh Hu 胡正杰 |
指導教授: | 陳景然(Ching-Jan Chen) |
關鍵字: | 全數位化線性穩壓器,快速暫態響應,估計負載變化量技術,系統晶片, Digital low-dropout regulator,fast transient response,ILOAD estimating technique,system-on-chip, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 全數位化的線性穩壓器被廣泛用於低電壓系統晶片之電源管理上。但是,全數位化的線性穩壓器的負載暫態響應受到採樣時鐘頻率的限制,導致過多的輸出下衝及緩慢的響應。本文提出了一種基於估計負載電流變化的新控制方法。此方法能夠準確地調整功率電晶體陣列並改善輸出下衝及暫態響應。提出的控制以TSMC-0.18μm製程技術實現積體電路。測量結果表明,響應時間僅為1.5個時脈週期,回穩時間僅需2.85個時脈週期,跟前人的作品相比,暫態響應時的輸出電壓下降值與穩定時間最接近理論極限。 Fully-digital low dropout regulator (D-LDO) is widely used in low-voltage system-on-chip (SOC) for power management. However, the load transient response of D-LDO is limited by the sampling clock frequency, resulting in excessive output voltage undershoot and slow response during transient. This thesis proposes a new control method for D-LDO based on load current change estimation. This method is capable of accurately adjusting the PowerMos array and improves the output voltage undershoot and load transient response. Besides, a figure-of-merit (FoM) to characterize the transient response of D-LDO is proposed. The proposed control was implemented in integrated circuit (IC) with TSMC-0.18um process. The measurement results show that the response time is only 1.5 clock cycles, and settling time is only 2.85 clock cycles. The output voltage drop and settling time at load step-up is closest to theoretical limit compared to other references. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/54662 |
DOI: | 10.6342/NTU202002233 |
全文授權: | 有償授權 |
顯示於系所單位: | 電機工程學系 |
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