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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Chen-Kai Hsu | en |
dc.contributor.author | 徐振凱 | zh_TW |
dc.date.accessioned | 2021-06-16T02:58:38Z | - |
dc.date.available | 2025-07-06 | |
dc.date.copyright | 2015-07-20 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-06 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/54467 | - |
dc.description.abstract | 類比數位轉換器是連接真實世界與離散運算領域的關鍵元件。
此篇論文提出了一個在九十奈米製程中實現的低功率管線式類比數位轉換器。然而放大器對於管線式類比數位轉換器來說,是一個非常重要且不可或缺的元件,另外為了使得管線式類比數位轉換器有良好的性能,放大器需要消耗相當可觀的功率消耗。管線式類比數位轉器使用n通道金氧半場效電晶體(NMOS)輸入,p通道金氧半場效電晶體(PMOS)為負載的單級放大器,已經在先前的成果[1]被證實,這種放大器可以提供更好的轉換效率。雖然這種放大器提升了功率效率,但是這種放大器帶來的負面效果是線性度的問題。在第一級解多位元是一個直接的解決辦法,然而這種做法會使得比較器的數目增加,並且對於比較器的偏移電壓容忍度更小。因此在此篇論文中,提出了粗級(coarse stage)輔助微級(fine stage)的概念。這種方式不僅僅在第一級解了四點五的位元而且也降低了比較器的數目,以及對於比較器的偏移電壓有更大的容忍度。 此次提出的類比數位轉換器已經於九十奈米製程中實現,核心電路所需要的晶片面積為0.15平方毫米。而此類比數位轉換器在一伏特的供給下,消耗了8.7毫瓦。實驗的結果顯示在輸入頻率為5.1-MHz下,信噪失真比(SNDR)約為57.23分貝,且在輸入頻率接近奈奎斯特頻率時,信噪失真比(SNDR)約為55.95分貝。另外在輸入頻率在整個奈奎斯特頻率的範圍內,信噪失真比(SNDR)皆高於55分貝。此篇論文的類比數位轉換器在每次轉換時所需要的能量約為42fJ。 | zh_TW |
dc.description.abstract | Analog-to-digital (A/D) converters which have been a communicator between the analog world and digital domain are indispensable building block in many systems.
In this dissertation, a 10-bit 400-MS/s pipeline ADC is proposed to achieve low power in a 90-nm CMOS technology. On the other hand, amplifiers, important and indispensable block of pipeline ADCs, consume significant power to ensure the performance. A prior art [1] employing a single-stage amplifier consisting of a NMOS differential pair with a PMOS load in pipeline ADCs has been proved that amplifier can provide better conversion-efficiency while achieving better FoM. Although the amplifier increases the power-efficiency, it also introduces the ineluctable linearity issue. A multi-bit front-end stage is a straightforward solution but the solution increases the number of comparators and makes the front-end stage more sensitive to the offset. Hence, this work proposes a coarse-stage-assisted front-end stage that not only resolves 4.5-bit in the first stage but also reduces the number of comparators and becomes less sensitive to the offset. The proposed ADC has been fabricated in a 90-nm standard CMOS technology which occupies 0.15mm2. The proposed ADC consumes 8.7 mW from a 1-V supply and achieves an SNDR of 57.23 dB at a 5.1-MHz input and 55.95 dB near Nyquist rate. It also achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band. The figure-of-merit (FoM) of the proposed ADC is 42 fJ/Conv. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T02:58:38Z (GMT). No. of bitstreams: 1 ntu-104-R01943019-1.pdf: 7189620 bytes, checksum: 04eea99c155f46fb3ea771437ef73067 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii Contents iv List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converters 4 2.1 Introduction 4 2.2 ADC Performance Metrics 4 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 4 2.2.2 Signal-to-Noise Ratio (SNR) 7 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 8 2.2.4 Effective Number-of-Bits (ENOB) 9 2.2.5 Spurious-Free Dynamic Range (SFDR) 9 2.2.6 Figure of Merit (FoM) 10 2.3 Architectures of Analog-to-Digital Converters 10 2.3.1 Flash Architecture 11 2.3.2 Two-Step and Sub-Ranging Architecture 12 2.3.3 Pipeline Architecture 13 2.3.4 Cyclic (Algorithmic) Architecture 15 2.4 Digital Error Correction 15 2.4.1 Out of Range Error 16 2.4.2 Over Range Error Correction 17 2.4.3 1.5-Bit Pipeline Stage 20 2.5 Summary 25 Chapter 3 A Single-Channel 10-bit 400-MS/s Pipeline ADC 26 3.1 Introduction 26 3.2 Proposed Architecture 28 3.3 Circuit Implementation 30 3.3.1 Input Sampling Network 31 3.3.2 Bootstrap Switch 32 3.3.3 Opamp Design 33 3.3.4 Capacitor-Interpolation subADC 36 3.3.5 subADC2 and subADC3 39 3.3.6 FlashADC 41 3.3.7 Comparator 42 3.3.8 Clock Buffer 44 3.4 Analysis of Proposed Stage 46 3.5 Power Analysis 53 3.6 Simulation Results 56 3.6.1 Post-Layout Simulation 56 3.6.2 Channel Gain Mismatch simulation 56 3.7 Experimental Results 59 3.7.1 Introduction 59 3.7.2 Measurement Setup 59 3.7.3 Print Circuit Board Design 60 3.7.4 Measurement Results 61 3.8 Summary 64 Chapter 4 Conclusions 65 Bibliography 66 | |
dc.language.iso | en | |
dc.title | 一個單通道十位元四億赫茲導管式類比數位轉換器 | zh_TW |
dc.title | A Single-Channel 10-bit 400-MS/s Pipeline ADC | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin),陳信樹(Hsin-Shu Chen),謝志成(Chih-Cheng Hsieh) | |
dc.subject.keyword | 高速,低功耗,管線式類比數位轉換器, | zh_TW |
dc.subject.keyword | High-speed,low-power,pipeline ADC, | en |
dc.relation.page | 68 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-07-06 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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