基於三維快閃記憶體之軟體控制部分區塊抹除設計

Abstract

隨著儲存裝置容量的快速成長，三維快閃記憶體已經成為市場主流趨勢。不同於以往二維快閃記憶體的管理，部分區塊抹除指令（稱為 sub-block erase operation）可以在三維快閃記憶體架構下減少額外的效能減損，但為了此指令解決伴隨而來的問題，我們提出了一個軟體控制部分區塊抹除的設計（稱為 sub-block erase with software isolation），這個機制不僅能不花額外的硬體成本就解決部分區塊抹除干擾的問題，更顯著地提升整體系統的效能及耐用度，最後，藉由一系列之實驗，我們驗證了所提出方法之有效性，並得到了令人振奮的結果。

The rapid growth of page number imposes the huge overhead on 3D flash-based storage devices since it will result in the large number of page copies once the garbage collection (GC) is invoked to reclaim free blocks. To reduce the GC overhead, a novel erase operation, called as “sub-block erase”, is proposed to enable the block erase operation to be divided into several sub-block erase operations and thus to reduce the number of copying live pages. However, the sub-block erase operation leads us to the new challenges since it might result in the serious interference and inner-block wear leveling problems. It becomes very important to resolve the negative impacts, such as serious interference, caused by adopting the sub-block erase technique without harming the performance of the sub-block erase operation. Such an observation motivates this work in the proposing of software isolation design to simultaneously resolve the reliability issue as well as exploit the characteristics of the sub-block erase for 3D flash memory. The proposed scheme was evaluated by a series of experiments with encouraging results.