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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
dc.contributor.author | Wei-Che Chang | en |
dc.contributor.author | 張偉哲 | zh_TW |
dc.date.accessioned | 2021-06-16T02:45:19Z | - |
dc.date.available | 2016-07-21 | |
dc.date.copyright | 2015-07-21 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-20 | |
dc.identifier.citation | [1] ITRS 2010: Taking on the energy challenge.
[2] Introduction to Finite Element Analysis, 2015. [3] B. Amelifard, F. Fallah, and M. Pedram. Reducing the sub-threshold and gate-tunneling leakage of sram cells using dual-vt and dual-tox assignment. In Design,Automation and Test in Europe, 2006. DATE ’06. Proceedings, volume 1, pages 1–6,March 2006. [4] D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on, pages 171–182, 2001. [5] T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout. An evaluation of high-level mechanistic core models. ACM Transactions on Architecture and Code Optimization (TACO), 2014. [6] A. Florea, C. Buduleci, R. Chis, A. Gellert, and L. Vintan. Enhancing the sniper simulator with thermal measurement. In System Theory, Control and Computing (ICSTCC), 2014 18th International Conference, pages 31–36, Oct 2014. [7] Y. Han, I. Koren, and C. M. Krishna. TILTS: A fast architectural-level transient thermal simulation method. J. Low Power Electronics, 3(1):13–21, 2007. [8] T. Hauck and T. Bohm. Thermal rc-network approach to analyze multichip power packages. In Semiconductor Thermal Measurement and Management Symposium,2000. Sixteenth Annual IEEE, pages 227–234, 2000. [9] M.-y. Hsieh, A. Rodrigues, R. Riesen, K. Thompson, and W. Song. A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration. SIGMETRICS Perform. Eval. Rev., 38(4):63–68, Mar.2011. [10] W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotspot: a compact thermal modeling methodology for early-stage vlsi design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 14(5):501–513, May 2006. [11] B. Kuo and F. Golnaraghi. Automatic control systems, 8th ed. 2002. [12] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the 42Nd Annual IEEE/ACM Inter-national Symposium on Microarchitecture, MICRO 42, pages 469–480, New York,NY, USA, 2009. ACM. [13] W. Liao, L. He, and K. Lepak. Temperature and supply voltage aware performance and power modeling at microarchitecture level. Computer-Aided Design of Inte-grated Circuits and Systems, IEEE Transactions on, 24(7):1042–1053, July 2005. [14] Y. Liu, R. Dick, L. Shang, and H. Yang. Accurate temperature-dependent integrated circuit leakage power estimation is easy. In Design, Automation Test in Europe Conference Exhibition, 2007. DATE ’07, pages 1–6, April 2007. [15] H. M. Moya-Cessa and F. Soto-Eguibar. Differential Equations: An Operational Approach chapter3. Rinton Press, 3 edition, 2011. [16] S. Pagani, H. Khdr, W. Munawar, J.-J. Chen, M. Shafique, M. Li, and J. Henkel. Tsp: Thermal safe power - efficient power budgeting for many-core systems in dark silicon. In Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014 International Conference on, pages 1–10, Oct 2014. [17] M. S. Santiago Pagani, Jian-Jia Chen and J. Henkel. Matex: Efficient transient and peak temperature computation for compact thermal models. 18th IEEE/ACM Design,Automation and Test in Europe (DATE), 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/54220 | - |
dc.description.abstract | 隨著現代多核技術在晶片上尋求更多的計算能力, 過熱問題在智慧手機、個人電腦和高端伺服器的晶片設計上是一個關鍵。因此,發展出各式各樣的能源管理演算法在不維背熱能的限制下來達成計算的要求,所有的能源管理機制不僅僅依賴對現下溫度測量,也需考量後面時間點上的溫度預測。然而,多數既存溫度預測演算法假設晶片上的漏電流功率消耗為常數,即並沒有意識在進階多核晶片中越來越重要的漏電流功率對溫度的影響。這篇論文探討溫度和漏電流功率消耗之間在電路上的回饋迴圈機制,並在多核平台上發展出對溫度敏銳的功率模型並提供精確快速的溫度預測。論文所提設的預測策略的好壞將從預測誤差和計算時間等方面來看,由基準測試 (benchmark)
來評估。實驗結果表示出我們的策略比相競爭的類似解法更加精準,能擁有更短的計算時間使得我們的策略適合即時的能源管理演算法。 | zh_TW |
dc.description.abstract | With the modern multi-core technology to explore more computing power in a chip, overheating is now a critical problem of chip designs for smart phones, personal computers, and high-end servers. Therefore, various power management algorithms are developed to meet the computing requirements without violating the thermal constraints, and all of the power management algorithms rely on not only the measurement of the current temperature but also the temperature estimation for the following time points. However, most of the existing temperature estimation algorithms assume that the leakage power consumption of a chip is a constant and are not aware of the impact of temperature on the leakage power consumption which is more and more significant in the advanced multi-core chips. This paper explores the feedback loop between the temperature and the leakage power consumption of a circuit and develops a temperature-aware power model to provide the accurate temperature estimation for multi-core platforms. The performance of the proposed estimation scheme is then evaluated with benchmark suites in terms of the estimation error and the computing time. The experimental results show that our scheme is more accurate than all of the competing solutions, and the short computing time also makes our scheme suitable for real-time power management algorithms. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T02:45:19Z (GMT). No. of bitstreams: 1 ntu-104-R02922031-1.pdf: 400776 bytes, checksum: c65fc9061bd41096143bdfa7603a28eb (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1 Power Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 RC Thermal Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Temperature in Transient State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Leakage Power Linearization . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Matrix Exponential Computation . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Acceleration in Root Finding . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 | |
dc.language.iso | en | |
dc.title | 具漏電功率考量之快速最高溫度計算 | zh_TW |
dc.title | Efficient Peak Temperature Computation with Leakage Power Consideration | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張哲維(Che-Wei Chang),黃柏鈞(Po-Chun Huang),劉邦鋒(Pang-Feng Liu),張原豪(Yuan-Hao Chang) | |
dc.subject.keyword | 漏電功率,矩陣指數,分析方法,能源效率,多核裝置, | zh_TW |
dc.subject.keyword | Leakage power,Matrix Exponential,Analytical method,Energy efficiency,Multi-core devices, | en |
dc.relation.page | 25 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-07-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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