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標題: | 基於稀疏表示法進行光場資料壓縮之硬體架構與實現 Hardware Architecture and Implementation for Sparse Representation Based Light Field Data Compression |
作者: | Yang-Ming Yeh 葉陽明 |
指導教授: | 盧奕璋 |
關鍵字: | 光場,相機陣列,超完備字典,資料壓縮,硬體設計, light field,camera array,overcomplete dictionary,data compression,hardware design, |
出版年 : | 2015 |
學位: | 碩士 |
摘要: | 四維光場資料是將來自同一場景,不同角度的光線利用相機陣列或光場相機記錄而成的影像資訊。然而,四維光場資料由於額外記錄了不同角度的入射光,因此也要付出相對應的紀錄空間,不管是在儲存上、處理上、或是傳輸上,都會造成相當的限制與不便。因此,如何有效率的將四維光場資料壓縮就成為了一個很重要的議題。 以Full HD, 的相機陣列為例,一組光場影像資料就需要將近600 MB的儲存空間,造成進行光場資料壓縮的過程也伴隨著耗時與龐大的計算量。在本篇論文中,我們設計了一組基於稀疏表示法進行光場資料壓縮的硬體加速裝置。藉助光場資料相似度高的特性,可將光場資料用超完備字典計算出對應的稀疏表示法後進行資料壓縮。在硬體設計上,我們首先利用資源分配的技術,最大化硬體元件的使用率,以限制積體電路面積;其次,我們將複雜與簡單的運算,以二個時域分別進行,再使用信號交換的技術做為橋樑銜接二個部分,並配合管線化及序列輸入並行輸出的架構設計,讓硬體速度最大化;最後,我們利用光場資料計算過程的可平行化性質,考慮充分使用雙倍資料率同步動態隨機存取記憶體架構的頻寬,提出最佳平行化手段,大幅提昇整體計算速度。 該硬體加速器使用TSMC 90 nm的製程設計,在400 MHz的運作頻率下,其加速可達軟體速度之7倍,晶片尺寸為2.592 mm2、消耗功率為154.6 mW。 We can use a camera array to record 4D light field data of a scene. The data contain the detailed information of intensities and directions of all captured rays. Because of the number of cameras used in a camera array, 4D light field data can take up a lot of disk space which may cause problems in storage, processing, and transmission. Thus, how to efficiently compress 4D light field data becomes an important research topic. Take a Full HD, camera array as an example, the light field data set would take up almost 600 MB of storage space. As a result, compressing light field data is both time-consuming and computationally expensive. In this thesis, we designed a hardware accelerator for sparse-representation-based light field data compression. Because of the high-similarity between light field data, we are able to employ an overcomplete dictionary to calculate the sparse representation of the light field data. When designing the hardware, first we apply the technique of resource allocation to maximize the hardware utilization and minimize the amount of hardware required. Next, we separate the computationally intensive part from the simple part. The two parts are assigned to two clock domains and connected with a handshaking technique. We also apply pipelining and the serial input/parallel output interface to maximize the speed of the hardware. Finally, by making the best use of the chosen DDR SDRAM bandwidth, we integrate two parallel cores on one chip to further improve the throughput. We implement the hardware accelerator using TSMC 90 nm technology. The chip can achieve 7 times speed up when compared with the software version. The chip area is 2.592 mm2, and its power consumption is 154.6 mW when operating at 400 MHz. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53864 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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