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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林浩雄 | |
dc.contributor.author | Fu-Wei Liu | en |
dc.contributor.author | 劉馥瑋 | zh_TW |
dc.date.accessioned | 2021-06-16T02:29:00Z | - |
dc.date.available | 2025-08-01 | |
dc.date.copyright | 2015-08-20 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-01 | |
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[30] Matthias Passlack, et al, “Interface State Analysis on Nonsilicon Semiconductors and The Role of Heterostructures,” 41st IEEE SISC, 2012. [31] Ning Li,Eric S. Harmon, James Hyland, David B. Salzman, T. P. Ma, Yi Xuan, and P. D. Ye, “Properties of InAs metal-oxide-semiconductor structures with atomic-layerdeposited Al2O3 Dielectric,” APPLIED PHYSICS LETTERS 92, 143507, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53755 | - |
dc.description.abstract | 本論文針對不同之處理改善氧化鋁(Al2O3)/砷化銦(InAs)之金氧半電容元件(Metal-oxide-semiconductor capacitor, MOS-Cap)之元件特性進行探討。透過三甲基鋁(Try-methyl-aluminum, TMA)前置處理搭配氨水(NH4OH)化學處理,在X射線光電子能譜分析中發現,成功有效的降低砷化銦之原生氧化物比例。再引入硝酸後氧化處理與沉積後退火處理後,有效減少了氧化層內之邊緣缺陷(Border trap),降低累積區頻散現象,並透過引入金屬後退火製程,改善費米能階釘札現象與磁滯現象。完成之元件,累積區頻散率為 1.42 %/dec、電容調變率為 31.4 %,與磁滯電壓變化為 150 mV。
透過累積區頻散之等效電路模型,我們成功擬合累積區之頻散電容,並且從中擬合出氧化層電容 COX;藉由擬合之氧化層電容,我們可由 G-V 求得室溫下最低之介面缺陷密度為 1.77*10^13 /eV*cm^2。在 5.3 奈米之等效氧化層厚度下,閘極電壓 ±1 V 內維持 2×10^-8 A/cm^2 低漏電流密度特性。 | zh_TW |
dc.description.abstract | In this study, we use different treatments to improve the characteristic Metal-oxide-semiconductor capacitor (MOS-Cap) of Al2O3 on InAs. We applied the Try-methyl-aluminum (TMA) pretreatment plus NH4OH chemical treatment before oxide growth, and the native oxide was effectively reduced, which is confirmed by XPS. We also applied the HNO3 post oxidation and post deposition annealing, and the border trap in oxide was effectively reduced and the accumulation frequency dispersion was suppressed. Then, we applied post metal annealing to improve the Fermi level pinning effect and hysteresis effect. Finally, the accumulation frequency dispersion value, the capacitance modulation, n-factor, and the hysteresis voltage of our device are 1.42 %/dec, 31.4 %, 0.14 and 150 mV.
By using the effective circuits of border trap, we can fit our capacitance in accumulation and fit our oxide capacitance. The interface trap density of 1.12×10^13 /eV*cm^2 was extracted by using the fitting oxide capacitance and G-V method. The low leakage current density of 2×10^-8 A/cm^2 at ±1 V was also obtained. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T02:29:00Z (GMT). No. of bitstreams: 1 ntu-104-R02943055-1.pdf: 4764046 bytes, checksum: 6e7e74fb84cc662f3a8492d29d6a77a2 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 目錄
中文摘要............................................................................................................................I Abstract.............................................................................................................................II 誌謝.................................................................................................................................III 圖目錄.............................................................................................................................VI 表目錄..........................................................................................................................VIII 第一章 導論.................................................................................................................... 1 1.1 前言.............................................................................................................1 1.2 研究動機.....................................................................................................2 1.3 論文架構.....................................................................................................6 第二章 理論介紹與實驗方法.........................................................................................7 2.1 金屬-氧化物-半導體元件電容之物理特性.........................................7 2.1.1 量測模型.............................................................................................7 2.1.2 累積區(Accumulationregion)..............................................................9 2.1.3 空乏區(Depletion region)..................................................................11 2.1.4 反轉區(Inversion region)..................................................................12 2.1.5 平帶情況...........................................................................................15 2.2 氧化層之缺陷電荷...................................................................................16 2.2.1 介面缺陷電荷(Interface trap charge, QIT).......................................16 2.2.2 固定氧化層電荷(Fixed Oxide charge, QF) .....................................17 2.2.3 氧化層缺陷電荷(Oxide trap charge, QOT) .....................................17 2.2.4 移動離子電荷(Mobile ion charge, QM) ..........................................17 2.3 介面缺陷密度分析...................................................................................18 2.4 原子層沉積系統(Atomic Layer Deposition, ALD)..................................20 2.5 X 射線光電子能譜理論..........................................................................22 2.6 Sentaurus TCAD模擬..............................................................................22 第三章 氧化鋁/砷化銦金氧半電容元件製作與分析..................................................23 3.1 試片製備與量測系統簡介.......................................................................23 3.2 三甲基鋁前置處理與氨水化學處理.......................................................25 3.3 氨水化學處理、硝酸後氧化處理與沉積後退火處理............................31 3.4 金屬後退火處理(Post Metal Annealing, PMA).......................................38 3.5 累積區之頻散分析...................................................................................46 3.6 氧化鋁/砷化銦金氧半電容元件之介面特性分析..................................54 3.7 漏電流特性分析.......................................................................................56 第四章 結論...................................................................................................................59 參考文獻.........................................................................................................................60 | |
dc.language.iso | zh-TW | |
dc.title | 氧化鋁/砷化銦金氧半電容元件特性改善與累積區頻散分析 | zh_TW |
dc.title | Characteristic Improvement of Al2O3/InAs Metal-Oxide-Semiconductor Capacitor and Analysis of Accumulation Frequency Dispersion | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 毛明華,陳敏璋,胡振國 | |
dc.subject.keyword | 砷化銦,氧化鋁,原子層沉積,金氧半電容,化學處理,邊緣缺陷,累積區頻散, | zh_TW |
dc.subject.keyword | InAs,Al2O3,ALD,MOS-Cap,Fermi level pinning,Chemical treatment,Border trap,Accumulation frequency dispersion, | en |
dc.relation.page | 63 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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