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標題: | 互補式金氧半導體功率放大器之功率結合技術以及改善回推效率與線性度研究 Research on Power Combining Technique and Improving Linearity and Back-off Efficiency for CMOS Power Amplifier |
作者: | Chun-Yen Chao 趙鈞彥 |
指導教授: | 林坤佑 |
關鍵字: | 毫米波,互補式金氧半導體,功率放大器,功率結合,回推效率,線性化, mmWave,CMOS,power amplifier,power combining,back-off,efficiency,linearization, |
出版年 : | 2015 |
學位: | 碩士 |
摘要: | 這篇論文共提出三個功率放大器,分別利用Doherty放大器、低頻二階項前饋、以及多路功率結合來提升放大器的回推效率、線性度以及輸出功率。
第一顆晶片是使用180奈米互補式金氧半導體製作一個操作在K 頻段且具有改善回推效率功能的改良式Doherty功率放大器。此功率放大器串接兩級放大器來達到更高的增益。在輸出級分成主路徑和附屬路徑,主路徑是AB類的共源極放大器,目的是為了在小訊號時有足夠的增益。附屬路徑是偏壓接近B類放大器的AB類疊接式放大器,目的是為了在大訊號時有不錯的增益,但在小訊號時消耗較少功耗,以提升放大器的回推效率。在功率分配的地方此電路使用了不均勻功率分配器以及相位補償傳輸線來提升回推效率和1-dB 壓縮點的輸出功率。根據在22 GHz量測的結果,此電路具有13.7 dB的小訊號增益,在飽和輸出功率時有17.2 dBm的輸出功率和24.8%的功率附加效率。而在1-dB 壓縮點有16.3 dBm的輸出功率和21.5%的功率附加效率。而在6-dB回推點有11.5%的功率附加效率。 第二顆晶片是使用90奈米互補式金氧半導體製作一個操作在60 GHz並利用低頻二階項前饋技術改善線性度的功率放大器。此功率放大器串接兩級放大器來達到更高的增益。電路包含主要放大器及線性器。主要放大器是由疊接組態組成,用來提供足夠的增益,而線性器產生與主路徑相同大小但相位相反的三階項電流來消除三階項電流。另外藉疊接組態電流鏡和直流位準移位器設計二階項電流以產生足夠的三階項電流。根據模擬結果,此電路具有15 dB的小訊號增益,在飽和輸出功率時有15.2 dBm的輸出功率和13%的功率附加效率。而在1-dB 壓縮點有13.9 dBm的輸出功率和11.5%的功率附加效率。三階項訊號在甜蜜點改善了大約20 dBc。根據量測結果,附屬路徑的直流電流和模擬有誤差,後文會附上偵錯結果。 第三顆晶片是使用90奈米互補式金氧半導體製作一個操作在E頻段並利用多路功率結合技術提升輸出功率的功率放大器。此功率放大器串接三級放大器來達到更高的增益。其中第二級使用16路功率結合,而第三級使用32路功率結合以輸出更多功率。在此兩級使用多路功率技術結合技術能使偏壓電路更簡單並提升操作頻寬。根據模擬結果,此電路在整個E頻段具有10~11.8 dB的小訊號增益,在飽和輸出功率時有15.3~16.1 dBm的輸出功率和6.8~8%的功率附加效率。而在1-dB 壓縮點有12.8~13.7 dBm的輸出功率。根據量測結果,小訊號增益在10 dB以下,和模擬有誤差。此外輸入端反射係數和模擬有差異,後文會附上偵錯結果。 In this thesis, a K-band modified Doherty power amplifier, a V-band PA using low-frequency IM2 feed-forward method, and a E-band PA using multi-way power combining technique are proposed to improve the back-off efficiency, linearity, and output power of CMOS power amplifiers respectively. First, a K-band modified Doherty power amplifier fabricated in 0.18-μm CMOS technology is proposed to improve the back-off efficiency. The proposed power amplifier consists of two stages for higher gain. The output stage is composed of main and auxiliary paths. The main path consists of common source topology and is biased at class-AB to provide enough gain at small signal. The auxiliary path consists of cascode topology and is biased at class-AB near class B to provide high gain at large signal and to save dc power consumption for small-signal operation. The uneven power splitter and phase-compensation line are used in power splitting to improve the back-off efficiency and OP1dB. According to the measurement results at 22 GHz, the proposed PA provides 13.7-dB small signal gain, 16.3-dBm OP1dB and 17.2-dBm Psat. The peak power-added-efficiency (PAE), PAE at OP1dB, and PAE at 6-dB back-off are 24.8%, 21.5%, and 11.5% respectively. Second, a low-frequency IM2 feed-forward method is used to improve the linearity of the 60 GHz CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of two stage for higher gain. The power stage consists of main amplifier and linearizer. The main amplifier consists of cascode topology to provide enough gain. The linearizer consists of two transistors to provide the same magnitude and inverse phase of IM3 current compared to the main amplifier to cancel the IM3 current at the output. The cascode current mirror and DC-level shifter are used to feed the IM2 current in the linearizer. According to the simulation results, the PA provides 15-dB small signal gain, 13.9-dBm OP1dB and 15.2-dBm Psat. The peak PAE and PAE at OP1dB is 13% and 11.5%, respectively. The IM3 signal is reduced about 20 dBc at sweet-spot. According to the measurement results, the dc current of the auxiliary path is different from that of the simulation result. The debug result is provided. Third, a multi-way power combining technique is used to increase the output power of the E-band CMOS power amplifier fabricated in 90-nm CMOS technology. The power amplifier consists of three stage for higher gain. The second and third stages are 16-way and 32-way combining respectively for higher output power. The power combining technique applied in the two stages can simplify the layout of bias circuit and achieve wideband matching. According to the simulation results from 71 to 86 GHz, the PA provides 10~11.8-dB small signal gain, 12.8~13.7-dBm OP1dB and 15.3~16.1-dBm Psat. The peak PAE is 6.8~8%. According to the measurement results, the gain is below 10 dB, and it is different from the simulation. Besides, the input return loss is different from the simulation result. The debug result is provided. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53155 |
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顯示於系所單位: | 電信工程學研究所 |
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