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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 高振宏(Cheng-Heng Kao) | |
dc.contributor.author | Han-Tang Hung | en |
dc.contributor.author | 洪漢堂 | zh_TW |
dc.date.accessioned | 2021-06-15T16:30:13Z | - |
dc.date.available | 2021-08-31 | |
dc.date.copyright | 2015-08-28 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-13 | |
dc.identifier.citation | [1] K. N. Tu, Microelectronics Reliability 51, 517-523 (2011) [2] K. N. Tu, H. Y. Hsiao, C. Chen, Microelectronics Reliability 53, 2-6 (2013) [3] J. H. Lau, in Electronic Components and Technology Conference (2010) [4] M. B. t. Wolfgang Arden, Patrick Cogez, Mart Graef, Bert Huizing, Reinhard Mahnkopf, Joachim Pelka, Jens-Uwe Pfeiffer, André Rouzaud, Marco Tartagni, Chris Van Hoof, Joachim Wagner, Cluster for Application and Technology Research in Europe on NanoElectronics (2011). [5] B. Banijamali, S. Ramalingam, H. Liu, K. Myongseob, in Electronic Components and Technology Conference (2012) [6] J. Asen Long Xin, M. Lai Chih, G. Jeff Chen Yi, H. Tan Kim, in Electronic Packaging Technology (2006) [7] K. Wei, B. Lin, J. Tai, in Electronic Packaging Technology and High Density Packaging (2011) [8] X. R. Zhang, W. H. Zhu, B. P. Liew, M. Gaurav, A. Yeo, K. C. Chan, in Thermal, 69 Mechanical Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (2010) [9] S. Lee, Y. X. Guo, C. K. Ong, in Electronic Packaging Technology Conference,(2005) [10] V. Fiori, Z. Xueren, T. Tong Yan, in Electronic Components and Technology Conference (2006) [11] Z. Tőkei, K. Croes, G. P. Beyer, Microelectronic Engineering 87, 348-354 (2010) [12] T. Suga, K. Otsuka, in Electronic Components and Technology Conference (2001) [13] H. Takagi, K. Kikuchi, R. Maeda, T. R. Chung, T. Suga, Applied Physics Letters 68, 2222 (1996) [14] T. H. Kim, M. M. R. Howlader, T. Itoh, T. Suga, Journal of Vacuum Science Technology A: Vacuum, Surfaces, and Films 21, 449 (2003) [15] T. Suga, Y. Takahashi, H. Takagi, B. Gibbesch, G. Elssner, Acta Metallurgica et Materialia 40, Supplement, S133-S137 (1992) [16] J. Gambino, J. Wynne, J. Gill, S. Mongeon, D. Meatyard, B. Lee, H. Bamnolker, L. Hall, N. Li, M. Hernandez, P. Little, M. Hamed, I. Ivanov, C. L. Gan, 70 Microelectronic Engineering 83, 2059-2067 (2006) [17] L. Jaesik, D. M. Fernandez, P. Myo, Y. Yen Chen, G. Shan. Components, Packaging and Manufacturing Technology, IEEE Transactions on 2, 964-970 (2012) [18] T. Osborn, A. He, N. Galiba, P. A. Kohl, Journal of The Electrochemical Society 155, D308 (2008) [19] A. He, T. Osborn, S. A. Bidstrup Allen, P. A. Kohl, Electrochemical and Solid-State Letters 9, C192 (2006) [20] H. C. Koo, R. Saha, P. A. Kohl, Journal of The Electrochemical Society 158, D698(2011) [21] H. C. Koo, R. Saha, P. A. Kohl, Journal of The Electrochemical Society 159, D319 (2012) [22] T. Osborn, N. Galiba, P. A. Kohl, Journal of The Electrochemical Society 156, D226 (2009) [23] K. Hyo-Chol, C. Lightsey, P. A. Kohl, Components, Packaging and Manufacturing Technology, IEEE Transactions on 2, 79-84 (2012) 71 [24] R. Saha, H. C. Koo, P. N. An, P. A. Kohl, Journal of the Electrochemical Society 159, D532-D537 (2012) | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52843 | - |
dc.description.abstract | 近年來,電鍍銅柱凸塊技術(Cu pillar bump)已經逐漸成熟並為業界所採⽤用,相 對於傳統的無鉛焊錫凸塊(Solder bump),銅柱凸塊具有更多的優點,其中適⽤用於更⼩小線距(fine pitch)的優勢使銅柱凸塊能提供更⾼高的接合密度;然⽽而,⽬目前銅柱凸塊的接合還是必須仰賴銲錫,隨著接點的線距不斷縮⼩小,⼩小體積的銲錫會在接合完成或使⽤用⼀一段時間後轉變為全介⾦金屬(full-IMC)的結構,當晶⽚片中柔軟的銲錫變成堅硬的銅及介⾦金屬時,將喪失吸收熱應⼒力的功能,此時應⼒力會轉⽽而集中在脆弱的low k 層造成剝離或是破壞進⽽而導致晶⽚片的失效。 因此,為了解決⽬目前所⾯面臨的挑戰並提供更好的接合,本研究開發了新的銅 柱接合技術,我們使⽤用可控制流場的無電鍍鎳磷藥⽔水去取代銲料並直接以鎳磷接合銅柱;在本論⽂文中,我們將廣泛⽤用於⽣生醫及製造微機電系統的微流道技術應⽤用在我們的技術中,將上下對準的試⽚片之間的縫隙製作成⼀一個密合的微流道,並利⽤用蠕動幫補來輸送藥⽔水進⼊入流道中以穩定地補充鎳離⼦子以提供上鍍。 此技術不但能夠解決銲料體積逐漸縮⼩小時所⾯面臨的困境,並且能提供⼀一個低 溫、低壓、低成本、及⾼高均勻性的製程,實驗結果顯⽰示使⽤用圓頂銅柱並利⽤用穩定的流場能夠提供⼀一個無孔洞及無縫隙的接合。結合的銅柱我們將使⽤用掃描式電⼦顯微鏡與光學顯微鏡協助分析,除此之外,為了消除試⽚片在研磨拋光時的破壞,我們使⽤用聚焦離⼦子束去進⾏行更深⼊入的觀察。 | zh_TW |
dc.description.abstract | Cu pillar bump offers more advantages comparing with conventional solder bump and is gradually becoming the next generation bumping technology for fine pitch applications. However, while the pitch decreases, shorter Cu pillar and smaller solder-cap volume pose adverse effects on reliability. The most critical issue is that the harder interconnection composed of Cu and full-IMC solder could degrade the mechanical stability of the Cu/low k structure due to the increase of thermal stress. In this study, to overcome this problem and optimize performance, we developed a new bonding technology that utilizes electroless Ni-P deposition with the application of controlled flow on the plating bath to replace solders and directly bond pillars. The PDMS technology, which is commonly used in biotechnology and for MEMS fabrication, was introduced into this thesis to fabricate the airtight microchannel between chips. Then, to supply adequate Ni ions, peristaltic pump was used to bump the electroless plating bath into the microchannel with controlled flow. This method provides many benefits including low-temperature and pressure-free process, low cost, high-uniformity, better thermal and electrical performance, and most importantly eliminating the issues arising from micro-solder bumps. The results show that dome-shaped CPBs with controlled flow present void-free and seamless interconnections. The bonded pillars in this thesis were analyzed by Scanning Electron Microscope (SEM) and Optical Microscope (OM). Besides, to further confirm and to avoid the damage during polishing with sandpapers, focused ion beam (FIB) was used for the observation. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T16:30:13Z (GMT). No. of bitstreams: 1 ntu-104-R02527009-1.pdf: 35100668 bytes, checksum: 286bd3713544b218b7dcaee991a5019e (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 摘要..............................................................................................................i Abstract......................................................................................................iii Contents......................................................................................................v List of Figures............................................................................................vii List of Tables.............................................................................................xii Chapter 1 Introduction.................................................................................1 1‐1 3D IC technology...................................................................................1 1‐2 Cu pillar bump (CPB).............................................................................5 1‐3 Bump‐less interconnections..................................................................8 1‐4 Electroless plating for Cu‐Cu interconnections....................................10 Chapter 2 Literature Reviews.....................................................................13 2-1 ElectrolessNi plating to compensate for bump height variation [17].....13 2-2 All‐Cu interconnections [18‐19]...........................................................20 2-3 Important parameters..........................................................................24 Chapter 3 Research Objectives.................................................................28 3-1 Low‐temperature and pressureless bonding process by electroless Ni-P plating.......................................................................................................28 3-2 High‐uniformity interconnections between chips using controlled flow...........................................................................................................29 Chapter 4 Experimental.............................................................................31 4-1 Test vehicle fabrication.......................................................................31 4-2 Fixture fabrication...............................................................................37 4-3 Electroless Ni‐P plating.......................................................................39 Chapter 5 Results and Discussion.............................................................43 5-1 The uniformity of plating using controlled flow.....................................44 5-2 Comparison between flat-topped and dome-‐shaped Cu pillars..........49 5‐3 The influence of pattern on the plating rate..........................................56 5-4 Batch process.....................................................................................61 Chapter 6 Conclusions...............................................................................66 6-1 Conclusions.........................................................................................66 6-2 Directions for future research..............................................................67 Chapter 7 References................................................................................68 | |
dc.language.iso | en | |
dc.title | 利⽤用控制流場的化學鎳所開發之接合技術 | zh_TW |
dc.title | Development of Cu-Cu Interconnections Using Controlled Flow Electroless Ni-P Plating | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳子嘉,顏怡文(Yee-wen Yen),何政恩 | |
dc.subject.keyword | 無電鍍接合,銅-銅接合, | zh_TW |
dc.subject.keyword | Electroless bonding,Cu-Cu interconnection, | en |
dc.relation.page | 71 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-13 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
顯示於系所單位: | 材料科學與工程學系 |
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