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標題: | 奈米類比電路之佈局合成自動化 Automatic Layout Synthesis for Nanometer Analog Circuit Designs |
作者: | Hung-Chih Ou 歐紘誌 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 實體設計,擺置,繞線,自對準雙圖樣微影,電子束微影,佈局相依效應,匹配,奈米類比積體電路, Physical Design,Placement,Routing,Self-Aligned Double Patterning,Electron Beam Lithography,Layout-Dependent Eects,Matching,Analog ICs, |
出版年 : | 2015 |
學位: | 博士 |
摘要: | 隨著積體電路製程的演進,奈米類比與數位電路的設計複雜度也急遽上升。近年來,佈局合成自動化技術已高度發展且普遍使用在奈米數位電路設計上;然而,現今之奈米類比電路設計仍然是使用耗時且繁瑣的手動方式進行佈局合成。最主要的原因是由於奈米類比電路之實體設計,特別是擺置及繞線階段,必須考慮許多複雜的限制條件以減少因電路佈局產生之不匹配、寄生效應及製程變異所造成的性能下降。除此之外,電路元件及連線之關鍵尺寸持續微縮也對類比電路的佈局合成帶來許多挑戰及需求。由於傳統光學微影之限制,自對準雙圖樣微影輔助電子束微影技術被視為最有可能將製程節點推向 20 奈米或以下的一種混合式微影技術;然而,圖樣變形及佈局相依型效應將有可能嚴重破壞電路之對稱性質及改變電路元件之臨界電壓及電子遷移率。因此,電路元件間的相對位置及佈局相依型效應的三個來源:井鄰近、氧化層長度及氧化層間距離將使得類比電路之擺置較數位電路困難許多。除此之外,更小的關鍵尺寸也將使得電路連線對於電流的不匹配及製程變異變得更加敏感,其會使得電路效能下降及降低可靠度,更進一步對類比電路帶來額外的繞線限制條件。因此,相較於已相當成熟之數位電路合成自動化,發展奈米類比電路之合成自動化技術面臨許多困難,並急需解決之道。 在這份論文中,我們針對奈米類比電路佈局合成中所面臨之關鍵課題提出了一個全新的佈局合成自動化引擎,其包含了數個新穎的擺置及繞線演算法。針對次世代自對準雙圖樣微影輔助電子束微影之混合微影技術,我們提出了一個考慮切除結構的擺置演算法以減少對稱原件間疊對誤差及電子束微影數之差異,並且確保電路之對稱性質不被破壞。接著,我們針對佈局相依效應的三個來源提出了一種新的解析擺置演算法,使電路之佈局合成能及早在擺置時有效的減輕佈局相依效應對臨界電壓及電子遷移率之變異影響。除此之外,在繞線階段我們也提出了一個考慮連線匹配的非均勻階層式繞線演算法,四種普遍使用於奈米類比電路之匹配方式:對稱、共質心、拓樸對稱及長度對稱在繞線時均可被嚴格遵守並且同時減少繞線線長、轉彎數、穿孔數及耦合效應。最後,為了展示同時擺置及繞線的可行性,我們也提出了一種可以同時考慮電流流動及電流密度等代表性限制條件之同時擺置及繞線演算法,使奈米類比電路之性能可以更加提升。實驗結果顯示我們所提出的擺置及繞線演算法對於奈米類比電路之佈局合成自動化是有效且有效率的;此外,我們所提出的演算法也可以滿足所有擺置及繞線之限制條件。 As integrated circuit (IC) technologies advance, design complexity grows dramatically for both analog and digital circuit designs. While automatic layout synthesis techniques are well developed and commonly used for digital circuits, most analog layout designs are still a manual, time-consuming, and tedious task today. The main reason is that the physical design of analog layout synthesis, especially the placement and routing, must consider numerous complex constraints and design rules to reduce the impacts of mismatches, parasitics, and process variations on circuit performance. Besides, the continuously scaling of the feature sizes on both devices and interconnects also brings substantial challenges and requirements for analog layout synthesis due to the limitation of conventional optical lithography technologies. Self-aligned double patterning (SADP) with complementary electron-beam lithography (EBL) has become one of the most promising hybrid-lithography techniques to push the process nodes to 20nm and beyond; however, unexpected pattern distortions and additional layout-dependent effects (LDEs) might significantly damage symmetry properties and vary the threshold voltage and mobility of analog devices. The device adjacency and the three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, make the analog placement much harder than that for digital ones. In addition, the smaller feature sizes also increase the sensitivity to current mismatches and process variations on interconnects, which might further degrade the circuit performance and reduce the reliability, and introduce additional routing constraints for analog circuits. As a result, developing automatic layout synthesis techniques, especially the placement and routing, for modern nanometer analog circuit designs encounters more difficulties than that for digital ones, and requires more innovative researches for a breakthrough. In this dissertation, we propose an automatic layout synthesis engine, which includes several novel analog placement and routing algorithms, to address the critical issues faced by modern nanometer analog circuit designs. To ensure the symmetry properties and manufacturability of modern analog circuit designs based on the SADP with complementary EBL, we present a cutting structure-aware placement algorithm for minimizing the differences of overlay errors and e-beam shots between symmetry modules. Then, we propose a layout-dependent-effects-aware analytical placement algorithm to mitigate the threshold voltage and mobility variations induced by the three major sources of LDEs while optimizing circuit performance earlier. To reduce the current mismatches and the sensitivity to process variations between two critical interconnects, we present a non-uniform multilevel routing algorithm to simultaneously consider four matching constraints, symmetry, common-centroid, topology-matching, and length matching while minimizing total wirelength, bend numbers, via counts, and coupling noise. To further reduce layout-induced parasitic impacts and achieving better circuit performance, we also demonstrate the feasibility of a simultaneous placement and routing algorithm by considering two most important constraints for analog designers, the current-flow and current-density constraints, during both the placement and routing stages. Experimental results show that our proposed analog layout synthesis algorithms are effective and efficient, and can satisfy all specified constraints. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52713 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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