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標題: | 基於差動拔靴帶式環形振盪器之低電壓全數位鎖相迴路 A Low Voltage All-Digital Phase-Locked Loop Based on Differential Bootstrapped Ring Oscillator |
作者: | Chi-Hao Wei 魏啟豪 |
指導教授: | 曹恆偉 |
關鍵字: | 鎖相迴路,時脈產生器,本地振盪器,時脈及資料恢復電路,相位抖動,相位雜訊,全數位鎖相迴路,環形振盪器,數位控制振盪器,二元式相位頻率偵測器,數位迴路濾波器,現場可程式化閘陣列, Phase-Locked Loop,Clock Generator,Local Oscillator,Clock and Data Recovery,Phase Jitter,Phase Noise,All-Digital Phase-Locked Loop,Ring Oscillator,Digitally-Controlled Oscillator,Bang-Bang Phase Frequency Detector,Digital Loop Filter,FPGA, |
出版年 : | 2016 |
學位: | 碩士 |
摘要: | 自從1930年第一個鎖相迴路 (Phase-Locked Loop, PLL) 被提出之後,鎖相迴路已有著十分廣泛的應用,如當作數位系統的時脈產生器 (Clock Generator)、通訊系統中的本地振盪器 (Local Oscillator)、時脈及資料恢復電路 (Clock and Data Re- covery, CDR)…等等。以上應用皆需要十分精準的頻率及相位同步,以滿足規格要求。所以設計一個適當操作頻率及頻寬,並具有低相位抖動 (Jitter)、低相位雜訊 (Phase Noise) 的鎖相迴路是十分重要的。
以往的鎖相迴路多為以類比電路為主,但因為數位電路具有面積小、功率消耗低且不易受製程變異所影響等優點,近幾年鎖相迴路的設計,除了振盪器以外,皆漸漸地朝向數位化前進,稱為全數位鎖相迴路 (All-Digital Phase-Locked Loop, ADPLL)。 本論文設計了一個5級差動拔靴帶式環形振盪器 (Ring Oscillator),此電路具有較大的輸出擺幅,使其在低電壓下具有良好的驅動能力,而雙端輸出的特性則使其具有更低的相位雜訊並且可擁有更廣泛的應用。我們將此振盪器配上高解析度的數位控制pMOS陣列形成了全數位鎖相迴路的數位控制振盪器 (Digitally- Controlled Oscillator, DCO),並和除頻器等周邊電路使用tsmc 90 nm CMOS 製程下線,下線的晶片面積為950 μm × 850 μm (含pad)。在輸出頻率為437 MHz時,其相位雜訊在1 MHz的offset處為-96.9 dBc/Hz。數位控制振盪器的功率消耗為225 μW (不含Buffer),整體功率消耗為2.3 mW (含Buffer)。 而Bang-Bang相位頻率偵測器 (Bang-Bang Phase Frequency Detector, BBPFD) 及數位迴路濾波器 (Digital Loop Filter, DLF) 則是使用Terasic DE2-115的Altera FPGA (Field- Programmable Gate Array) 電路板配合晶片來一起驗證。在輸入的參考頻率為6.5 MHz,輸出頻率為416 MHz時,其相位雜訊在1 MHz的offset處為-102.1 dBc/Hz。 Since the first phase-locked loop was proposed in 1930, many applications have been found with phase-locked loops, e.g., the clock generators in digital circuits, local oscillators of communication systems, clock and data recovery circuits, and so on. Phase-locked loops have to achieve accurate phase and frequency synchronization in order to meet the specifications. Therefore, it is very important to design a phase-locked loop which has proper operating frequency range with low phase jitter and low phase noise. Analog phase-locked loops were usually adopted in traditional approach. On the other hand, the digital circuits have many advantages such as low area, low power, and good portability. The research of phase-locked loops are gradually moving toward fully- digitized in recent years except oscillators. It is known as all-digital phase-locked loop. This thesis proposes a 5-stage differential bootstrapped ring oscillator. Its large output swing makes it have good driving capability in low supply voltage. On the other hand, the differential output makes it have low phase noise and much wider applications. This oscillator is then combined with a high-resolution digitally-controlled pMOS array as the digitally-controlled oscillator (DCO) of an all-digital phase-locked loop, and it is fabricated in tsmc 90 nm CMOS technology with frequency divider and other peripheral circuits. The chip area is 950 μm × 850 μm (with pad). When the output frequency is 437 MHz, the phase noise of the digitally-controlled oscillator alone is -96.9 dBc/Hz at 1 MHz offset. The consumption of digitally-controlled oscillator is 225 μW (without buffer), and the total power consumption of the chip is 2.3 mW (with buffer). The chip is verified with the bang-bang phase frequency detector and the digital loop filter which were synthesized on the Terasic DE2-115 Altera FPGA board. When the reference frequency is 6.5 MHz and the output frequency is 416 MHz, the phase noise of the all-digital phase-locked loop is -102.1 dBc/Hz at 1 MHz offset. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51533 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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