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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51159完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | |
| dc.contributor.author | Yu-Chen Huang | en |
| dc.contributor.author | 黃于真 | zh_TW |
| dc.date.accessioned | 2021-06-15T13:26:23Z | - |
| dc.date.available | 2021-04-06 | |
| dc.date.copyright | 2016-04-06 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-03-25 | |
| dc.identifier.citation | [1] ISPD 2015 Blockage-Aware Detailed Routing-Driven Placement Contest, http://www.ispd.cc/contests/15/ispd2015contest.html.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51159 | - |
| dc.description.abstract | 電子束微影為極具發展性之下世代微影技術其中的一項，因其可突破傳統光學微影所受到的解析度限制，然而，若要將電子束微影應用於量產製作，仍舊有相當多的挑戰需要被克服，其中一項即為電子束微影之霧化效應。在電子束微影的過程中，電子會在阻劑及基質中散射，造成多餘的曝光，其分布範圍可達數毫米以上。這些多餘曝光將造成關鍵尺寸的不一致性與線端的失真，進一步造成積體電路的缺陷。過去的研究提出，可藉由裝置電子吸收盤或調整曝光劑量來修正霧化效應，然而電子吸收盤無法完全解除電子二次散射的問題，曝光劑量的調整則需耗費大量時間。由於電子束霧化效應的影響範圍極廣，故此效應之分布與圖樣密度有密切關係，又圖樣密度主要於電路擺置階段中決定，因此，本論文提出第一個於電路擺置階段考慮霧化效應的演算法，在電路擺置時最小化霧化效應之變異值，進而藉由降低一均勻劑量來修正霧化效應。此演算法首先將標準元件視為可移動之霧化效應來源，再使用快速高斯轉換於解析式擺置器內估算晶片各處之額外曝光值，並以各測量點之霧化效應變異值導引標準元件至適當位置。實驗結果顯示此演算法能在維持繞線長度的品質下，有效降低霧化效應之變異值達百分之十以上。 | zh_TW |
| dc.description.abstract | Electron beam lithography (EBL) is one of the most promising candidates among next-generation lithography (NGL) technology to conquer the resolution limit of the optical lithography. However, there are still challenges for EBL to be applied practically in massive production. One of those obstacles is the fogging effect. It is caused by re-scattered electrons in the resist and the substrate, and increases the undesired exposure in a wide range which could be up to millimeter scale. As a result, the fogging effect gives rise to the non-uniformity of critical dimension and line end distortion. Prior endeavors have been proposed to decrease the fogging effect by adding an absorber plate or compensating the exposure dosage. However, those approaches cannot completely solve the problem and the scalability is not as good as required for massive production. Due to the wide influential range, the fogging effect is related to the pattern distribution, which is mainly determined during placement. In this thesis, we propose the first algorithm to tackle the fogging effect in the placement stage. The idea is to minimize the variation of the fogging effect in our placement algorithm, and thus the fogging effect can be corrected by reducing a dosage uniformly over the whole chip. We first model standard cells into movable sources of the fogging effect, and adopt the fast Gauss transform to approximate the extra exposure iteratively in our analytical placer. The variation of the fogging effect at different evaluation points then guides the cells to appropriate positions. Experimental results show that our algorithm can effectively reduce the fogging variation by over 10%, while maintaining the quality of wirelength. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T13:26:23Z (GMT). No. of bitstreams: 1 ntu-105-R02943100-1.pdf: 3372858 bytes, checksum: e8885edbfdfb6b5aafe5ab3c550b93c6 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | Chapter 1. Introduction 1
1.1 Electron Beam Lithography . . . . . . . . . . . . . . 1 1.2 VLSI Circuit Placement . . . . . . . . . . . . . . . 5 1.3 Related Work . . . . . . . . . . . . . . . . . . . . 10 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . 12 1.5 Our Contributions . . . . . . . . . . . . . . . . . . 14 1.6 Thesis Organization . . . . . . . . . . . . . . . . . 14 Chapter 2. Preliminaries 15 2.1 Analytical Placement . . . . . . . . . . . . . . . . 15 2.2 Fast Gauss Transform . . . . . . . . . . . . . . . . 20 2.3 Problem Formulation . . . . . . . . . . . . . . . . . 27 Chapter 3. Placement Considering Fogging Eect 29 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . 29 3.2 Fogging Source Model . . . . . . . . . . . . . . . . 30 3.3 Model Eectiveness . . . . . . . . . . . . . . . . . 33 3.4 Global Placement . . . . . . . . . . . . . . . . . . 35 3.5 Legalization . . . . . . . . . . . . . . . . . . . . 38 3.6 Fogging-Aware Cell Swapping . . . . . . . . . . . . . 41 Chapter 4. Experimental Results 44 4.1 Experimental Setup . . . . . . . . . . . . . . . . . 44 4.2 Experimental Results . . . . . . . . . . . . . . . . 45 4.3 Experimental Analysis . . . . . . . . . . . . . . . . 48 Chapter 5. Conclusions and Future Work 53 | |
| dc.language.iso | en | |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 電子束微影 | zh_TW |
| dc.subject | 霧化效應 | zh_TW |
| dc.subject | 可製造性 | zh_TW |
| dc.subject | 電路擺置 | zh_TW |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 電子束微影 | zh_TW |
| dc.subject | 霧化效應 | zh_TW |
| dc.subject | 可製造性 | zh_TW |
| dc.subject | 電路擺置 | zh_TW |
| dc.subject | Physical Design | en |
| dc.subject | Physical Design | en |
| dc.subject | Placement | en |
| dc.subject | Manufacturability | en |
| dc.subject | Fogging Effect | en |
| dc.subject | Electron Beam Lithography | en |
| dc.subject | Placement | en |
| dc.subject | Manufacturability | en |
| dc.subject | Fogging Effect | en |
| dc.subject | Electron Beam Lithography | en |
| dc.title | 考慮電子束霧化效應之電路擺置 | zh_TW |
| dc.title | Placement Considering the Electron Beam Fogging Effect | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江介宏,江蕙如,方劭云 | |
| dc.subject.keyword | 實體設計,電子束微影,霧化效應,可製造性,電路擺置, | zh_TW |
| dc.subject.keyword | Physical Design,Electron Beam Lithography,Fogging Effect,Manufacturability,Placement, | en |
| dc.relation.page | 62 | |
| dc.identifier.doi | 10.6342/NTU201600147 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-03-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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