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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
dc.contributor.author | Chien-Chung Ho | en |
dc.contributor.author | 何建忠 | zh_TW |
dc.date.accessioned | 2021-06-15T13:06:44Z | - |
dc.date.available | 2026-12-31 | |
dc.date.copyright | 2016-07-26 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-07-01 | |
dc.identifier.citation | [1] Flash File System. US Patent 540,448. In Intel Corporation.
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[49] Suman Nath and Aman Kansal. FlashDB: Dynamic Self-tuning Database for NAND Flash. Technical report, Microsoft Research (MSR), November 2006. [50] Sai-Tung On, Hai-Bo Hu, Yu Li, and Jian-Liang Xu. Lazy-update B+-tree for flash devices. Mobile Data Management, IEEE International Conference on, 0:323–328, 2009. [51] Veera Papirla and Chaitali Chakrabarti. Energy-Aware Error Control Coding for Flash Memories. In the ACM/IEEE Design Automation Conference (DAC), July 2009. [52] Chan-Sul Park and Tae-Hee Han. Fast mounting method for NAND flash memory file system using offset information. In ICACT’10, the 12th International Conference on Advanced Communication Technology, volume 1, pages 675–679, Feb. 2010. [53] Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, and Jin-Soo Kim. Energy-Aware Demand Paging on NAND Flash-based Embedded Storages. In the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2004. [54] D. Park, B. Debnath, and David Hung-Chang Du. CFTL: A Convertible Flash Translation Layer Adaptive to Data Access Patterns. In SIGMETRICS’10, pages 14–18, June 2010. [55] Junkil Ryu and Chanik Park. Fast initialization and memorymanagement techniques for log-based flash memory file systems. In Proceedings of the 3rd International Conference on Embedded Software and Systems, ICESS ’07, pages 219–228, Berlin, Heidelberg, 2007. Springer-Verlag. [56] Samsung. K9F1G08U0M 1Gb NAND MLC Flash Memory Datasheet, 2004. [57] Samsung Electronics. K9F1208U0M 64M * 8 Bit NAND Flash Memory Data Sheet, 2001. [58] Samsung Electronics. K9F2808U0B 16M * 8 Bit NAND Flash Memory Data Sheet, 2001. [59] Samsung Electronics. K9K8G08U0M 1G * 8 Bit NAND Flash Memory Data Sheet, 2005. [60] Samsung Electronics. OneNAND Features and Performance, 11 2005. [61] Samsung Electronics. K9GAG08U0M 2G x 8bit NAND Flash Memory Data Sheet, September 2006. [62] Samsung Electronics. KFW8G16Q2M-DEBx 512M x 16bit OneNAND Flash Memory Data Sheet, 09 2006. [63] Jing Chen Sheng-Jie Syu. An Active Space Recycling Mechanism for Flash Storage Systems in Real-Time Application Environment. 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Application (RTCSA’05), pages 53–59, 2005. [64] Dmitry Shmidt. Technical note: Trueffs wear-leveling mechanism (tn-doc-017). Technical report, M-System, 2002. [65] Spectek. NAND Flash Memory MLC, 2003. [66] Michal Spivak and Sivan Toledo. Storing a persistent transactional object heap on flash memory. In LCTES ’06: Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems, pages 22–33, 2006. [67] STMicroelectronics. NAND08Gx3C2A 8Gbit Multi-level NAND Flash Memory, 2005. [68] David Woodhouse. JFFS: The Journalling Flash File System. In Ottawa Linux Symposium, 2001. [69] Chin-Hsien Wu, Li-Pin Chang, and Tei-Wei Kuo. An Efficient B-Tree Layer for Flash-Memory Storage Systems. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/50922 | - |
dc.description.abstract | 為了滿足使用者對於快閃記憶體儲存裝置不斷成長的容量需求,3D 快閃記憶體以及MLC (Multi-Level Cell) 快閃記憶體技術已經廣泛被市場以及供應商採用,使得快閃記憶體晶片容量可以持續地透過堆疊以及壓縮的方式不斷增加。然而,如此快速的記憶體需求增長以及堆疊壓縮製程雖然帶來了快速增加容量的優點,同一時間也對快閃記憶體帶來了不好的影響,像是效能變差、擴充性不佳、可靠性變差的議題。這些都會使得未來再設計超大容量的快閃記憶體儲存裝置上帶來相當大的挑戰。本論文提出一個只需極少量主記憶體空間就能有效管理龐大容量的快閃記憶體,使得快閃記憶體容量增長不會因為記憶體空間不足而造成效能大受影響。第二的部分我們從超大容量快閃記憶體在建置上因為特性不斷變化而使得設計成本以及開發成本上會有巨大的困難,也因此在這裡我們提出以模組化晶片去建置固態硬碟,使得新晶片上的不同特性差距可以利用模組化晶片所提共的統一存取介面來克服。同時本論文也提出了一個可以改變資料存取特性的管理方法,使得模組化晶片上為人詬病的讀寫效能問題能被克服。 | zh_TW |
dc.description.abstract | To meet the growing capacity needs of flash-based storage systems, 3D (NAND) and multi-level-cell (MLC) flash memory are widely considered the promising alternative to continuously scale up the capacity of flash chips. However, the rapid growth of the capacity of a flash-memory storage device imposes challenges on the designs of ultra-scale flash memory storage, such as performance, scalability and reliability issues. This dissertation proposes methodologies from different view points to resolve design issues caused by the keep-changing characteristics of flash memory. We first propose a hybrid index design that over DRAM and flash memory simultaneously to solve the performance issue. The proposed idea can achieve excellent performance even the DRAM space of the evaluated system is very limited. Today’s SSD controllers are facing problems as flash is continuously and frequently updated. Such a phenomenon introduces large cost and heavy bus load on the design of SSD controllers. As a result, a module design to construct an eMMC-enabled SSD is then proposed to solve the scalability issue. An access pattern reshaping design is proposed to simultaneously consider the I/O performance and properties of eMMC-enabled SSDs. With the idea of eMMC-enabled SSD, industry and vendor might has another option to face the problem. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T13:06:44Z (GMT). No. of bitstreams: 1 ntu-105-F99922110-1.pdf: 2096233 bytes, checksum: 360fbd75388439b78ba15fe7dc9557ac (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | Acknowledgment iv
Abstract in Chinese vi Abstract vii Contents ix List of Figures xiii List of Tables xiv 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 Research Issues on Flash Memory . . . . . . . . . . . . . . . . . 6 1.3.2 Existing Flash-Translation-Layer Implementations . . . . . . . . 8 1.4 Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 A DRAM-Flash Index for Native Flash File Systems 15 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Hybrid Index Design over DRAM and Flash Memory . . . . . . . . . . . 20 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.2 The Design of a Hybrid Index Tree . . . . . . . . . . . . . . . . 22 2.2.3 Cost-oriented Space Management . . . . . . . . . . . . . . . . . 26 2.2.4 System Initialization and Crash Recovery . . . . . . . . . . . . . 29 2.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2 System performance . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.3 Space-performance Trade-off and Effects of Reclaiming Weights . 35 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Access Pattern Reshaping for eMMC-enabled SSDs 40 3.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 Access Pattern Reshaping for eMMC-enabled SSDs . . . . . . . . . . . . 45 3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.2 Address Reshaping Write Strategy . . . . . . . . . . . . . . . . . 47 3.2.3 EBA Space Reclamation . . . . . . . . . . . . . . . . . . . . . . 52 3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 57 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4 Concluding Remarks 61 4.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Bibliography 65 Curriculum Vitae 75 Publication List 77 | |
dc.language.iso | en | |
dc.title | 超大規模快閃記憶體儲存裝置之效能、模組化和可靠度技術探討 | zh_TW |
dc.title | Enabling Ultra-Scale Flash Memory Storage in the Post-Gigabyte Era: Performance, Scalability and Reliability | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 博士 | |
dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
dc.contributor.oralexamcommittee | 楊佳玲(Chia-Lin Yang),洪士灝(Shih-Hao Hung),施吉昇(Chi-Sheng Shih),賴尚宏(Shang-Hong Lai),曾煜棋(Yu-Chee Tseng) | |
dc.subject.keyword | 儲存系統,超大規模快閃記憶體,效能,可靠性,擴充性, | zh_TW |
dc.subject.keyword | storage system,ultra-scale flash memory,performance,reliability,scalability, | en |
dc.relation.page | 79 | |
dc.identifier.doi | 10.6342/NTU201600610 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-07-01 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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