請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/50305完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥(Sy-Yen Kuo) | |
| dc.contributor.author | Ming-Ko CHO | en |
| dc.contributor.author | 卓旻科 | zh_TW |
| dc.date.accessioned | 2021-06-15T12:35:42Z | - |
| dc.date.available | 2018-08-24 | |
| dc.date.copyright | 2016-08-24 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-07-30 | |
| dc.identifier.citation | [1] Ieee standard for verilog hardware description language. IEEE Std 1364-2005 (Revi- sion of IEEE Std 1364-2001), page 108, 2006.
[2] K. H. Chang and C. Browy. Improving gate-level simulation accuracy when unknowns exist. In Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, pages 936–940, June 2012. [3] T. Junttila and P. Kaski. Engineering an efficient canonical labeling tool for large and sparse graphs. In D. Applegate, G. S. Brodal, D. Panario, and R. Sedgewick, edi- tors, Proceedings of the Ninth Workshop on Algorithm Engineering and Experiments and the Fourth Workshop on Analytic Algorithms and Combinatorics, pages 135–149. SIAM, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/50305 | - |
| dc.description.abstract | 未知值(Xs)可能在存在於未初始化暫存器器或是未通電的區塊內。
此種未知值可能會造成X-bugs,X悲觀或X樂觀。 當我們要解決這些X-bugs時,我們必須從暫存器的輸入端追溯回前級的元件。 透過解析元件功的輸入功能,我們可以得到元件的額外資訊,進而篩選出我們進一步追溯下去的輸入端,可以有效減少搜尋的空間。 這篇論文提出了一個分析序向使用者定義元件(sequential UDPs)的方法,其中使用到模式匹配及對稱性的技巧。 我們在商業軟體上的實驗結果顯示出此方法十分有效且快速。 | zh_TW |
| dc.description.abstract | Unknown value (Xs) may exist in a design due to uninitialized registers or blocks that are powered down.
Such Xs may cause X bugs known as X-pessimism and X-optimism. When we are solving X-pessimism problems, we have to trace along the fan-ins of a register's input. By reconstructing cell functions, the procedure above will get extra information of the cells encountered and thus can reduce its search space. To analyze the cell properly and provide the exact cell functions information, we proposed a methodology including pattern matching and symmetry detecting techniques which reveals the functional information about SUDP inputs. Our experimental results on commercial designs show that the proposed method is effective and efficient. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T12:35:42Z (GMT). No. of bitstreams: 1 ntu-105-R03921057-1.pdf: 396339 bytes, checksum: 9fbd1cc0436c11ab1eb51fc28a2bd895 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii 1 Introduction 1 2 Background 3 2.1 User-DefinedPrimitives(UDPs) ...................... 3 2.2 Symmetry.................................. 4 3 Methodology 6 3.1 PatternMatching .............................. 6 3.2 SymmetryDetection ............................ 7 4 Pattern Matching 8 4.1 EntryofthePrimitiveTable ........................ 8 4.2 IterationThroughtheTable......................... 8 4.3 InputType.................................. 9 4.4 JKFlip-flopHandling............................ 10 5 Symmetry Detection 11 5.1 Algorithm.................................. 11 5.2 Proof .................................... 13 6 Experimental Result 18 6.1 CaseStudies................................. 18 6.2 SymmetryDetection ............................ 18 7 Conclusion 20 Bibliography 21 | |
| dc.language.iso | en | |
| dc.subject | 對稱性 | zh_TW |
| dc.subject | 未知值 | zh_TW |
| dc.subject | 序向使用者定義單元 | zh_TW |
| dc.subject | 閘位準邏輯模擬 | zh_TW |
| dc.subject | graph symmetry | en |
| dc.subject | sequential user-defined primitives | en |
| dc.subject | Gate-level logic simulation | en |
| dc.subject | X-pessimism | en |
| dc.subject | X-pessimism | en |
| dc.subject | Gate-level logic simulation | en |
| dc.subject | sequential user-defined primitives | en |
| dc.subject | graph symmetry | en |
| dc.title | 使⽤模式匹配及對稱性解析單位元件功能 | zh_TW |
| dc.title | Reconstructing Cell Functions from Sequential Truth Tables Using Pattern Matching and Symmetries | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆(Chin-Laung Lei),顏嗣鈞(Hsu-chun Yen),陳英一(Ing-Yi Chen),陳俊良(Jiann-Liang Chen) | |
| dc.subject.keyword | 未知值,閘位準邏輯模擬,序向使用者定義單元,對稱性, | zh_TW |
| dc.subject.keyword | X-pessimism,Gate-level logic simulation,sequential user-defined primitives,graph symmetry, | en |
| dc.relation.page | 21 | |
| dc.identifier.doi | 10.6342/NTU201601621 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位: | 電機工程學系 | |
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