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標題: | 使用相位注入技術之寬頻帶多相位延遲鎖相迴路 A Wide-Range Multi-Phase DLL with phase insertion architecture |
作者: | Bing-Feng Lin 林柄灃 |
指導教授: | 陳中平(Chung-Ping Chen) |
關鍵字: | 延遲鎖相迴路,多相位,寬頻帶,相位注入,數位相位選擇器,離散式延遲鎖相迴路, delay-locked loop,multi-phase,wide range,phase insertion,digital phase selector,distributed DLL, |
出版年 : | 2010 |
學位: | 碩士 |
摘要: | 為了達成低功率的消耗,本論文提出一個功率調節系統來控制不同的操作頻率狀況。為了達到這個目的,我們需要一個寬頻代的時脈產生器,為了實現一個寬頻帶的延遲鎖相迴路,我們需要許多條不同延遲時間的電壓控制延遲時間帶,來達到寬頻帶的操作。
在本論文中,我們提出了一個新架構的延遲鎖相迴路來產生寬頻帶時脈產生器,在這個架構之中,包含了一個數位的相位選擇器以及類比的延遲鎖相迴路。數位相位選擇器可以用來產生相位,所以我們就不需要多條的電壓控制延遲帶。而後方的類比延遲鎖相迴路是使用離散式延遲鎖相迴路的架構並且加以變化改良。在數位的相位選擇器中,我們會依照輸入的頻率來選出對應到的相位。在相位選擇器選擇出對應的相位之後,後端的類比延遲鎖相迴路會將各個相位獨立鎖定。 在本論文針對TSMC 90nm製程提出兩個相位注入延遲鎖相迴路,一為單端輸入之500MHz-6GHz之三相位注入延遲鎖像迴路,其消耗功率為33mW且其占用的面積是0.148mm2 ,抖動峰值為6.915ps,抖動方均根值為1.78ps,操作在6GHz的時候,最大的相位誤差是1.78ps,另一為雙端輸入之2.27-8GHz之六相位延遲鎖相迴路,其消耗功率為28mW且其占用的面積是0.25mm2 ,抖動峰值為6.62ps,抖動方均根值為1.10ps,操作在6GHz的時候,最大的相位誤差為2.015ps。 To achieve low power consumption, this thesis proposes a power management system to control the different operation situations. For this purpose, a wide-range clock generator is necessary, and in order to realize the wide range DLL for clock generator, various VCDL with different delay times are needed. In this thesis, a novel architecture is proposed to generate wide-range multi-phase DLL. This architecture includes digital phase selector and analog DLL. Digital phase selector to generate the phases, there is no need to have various VCDL. Analog DLL is based on distributed DLL architecture. Digital phase selector will choose the corresponding phases depend on input frequency. After the phase selector selects the corresponding phases, Analog DLL is used to lock each phase independently. Two DLLs are proposed in this thesis and are fabricated in TSMC 90nm CMOS technology. The first is a three-phase output Phase insertion DLL operating from 500MHz to 6GHz which dissipates 33mW and occupies a 0.148mm¬¬¬2 active area. The rms jitter has been measured to be 1.169ps, peak-to-peak jitter is 6.915ps and maximum phase error is 1.78ps.The second is a differential input and six-phase output Phase insertion DLL operating from 2.27GHz to 8GHzwhich dissipates 28mW from 1.2v-power supply and occupies a 0.25mm¬¬¬2 active area. The rms jitter of the output signal has been measured to be 1.10ps, and peak-to-peak jitter is 6.63ps, maximum phase error is 2.015ps when operating in 6GHz. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48690 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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