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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 簡韶逸(Shao-Yi Chien) | |
| dc.contributor.author | Tse-Wei Chen | en |
| dc.contributor.author | 陳則瑋 | zh_TW |
| dc.date.accessioned | 2021-06-15T07:08:22Z | - |
| dc.date.available | 2015-11-15 | |
| dc.date.copyright | 2010-11-15 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-11-01 | |
| dc.identifier.citation | [1] S.-Y. Chien, S.-Y. Ma, and L.-G. Chen, “Efficient moving object segmentation algorithm using background registration technique,” IEEE Transactions
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48685 | - |
| dc.description.abstract | 近年來由於半導體製程技術的發展，愈來愈多的應用出現在消費性電子產品之中。各種不同功能的電子產品，例如攜帶電話，數位相機，掌上型電腦，也在時代的趨勢下逐漸整合成一種具備各種功能的完整系統。同時，記憶體的容量不斷地提昇，但是其價格與生產成本卻是不斷下降。可以預見地，未來傳統的硬碟極有可能會被取代成為擁有更大容量的先進記憶元件。在擁有了極大量的資料儲存空間之後，儲存多媒體資訊就會成為一大用途，也使得自動化的多媒體分析成為重要的應用。在消費性電子產品的嵌入式系統之中，傳統的中央處理器，以及客製化的數位積體電路無法同時滿足多媒體分析演算法的彈性以及效能須求。因此，在下一代的應用之中，發展一套新的軟硬體設計方式是很重要的。
針對多媒體內容分析的須求，作者提出了一套新的設計及實作方式。從演算法設計，硬體架構分析，軟硬體共同設計，以及單晶片系統實作，發展出一系列的方法，並且適合應用於各種消費性電子產品之中，例如行動式裝置。為了有效地分析多媒體的內容，「特徵截取」以及「機器學習」是不可或缺的步驟。現今有各種機器學習的演算法被應用著，包括監督式學習、非監督式學習……等。這些演算法被視為多媒體內容分析的重要組成元素。因此，作者提出了高效能的客製化硬體架構以及可重組化的多功能硬體架構來支援「機器學習」並且處理多媒體的內容分析。高效能客製化硬體架構的部份，由於K平均分群法是機器學習中非監督式學習的一個非常重要之演算法，作者針對此方法做了很多的分析與探討。論文中提出四種不同的K平均分群法架構，分別適用於不同的應用環境，並且展示了結合所提出硬體架構的一個軟硬體共同設計系統，用以執行自動化的相片檢索功能。可重組化的多功能硬體架構部份，為了支援不同的機器學習演算法，兩種不同特色的單晶片系統也在本論文中被提出。這兩種系統藉由密集平行化的串流處理器架構處理大量的影像「特徵截取」運算，也可以基於可重組化的硬體架構及高頻寬的記憶單元，支援不同「機器學習」演算法的運算，包括K平均分群法、K最近鄰居分類器、高斯模型分類器、支援向量機、類神經網路……等。 簡而言之，本論文提出了兩種對於視訊以及影像的切割演算法，四種不同的K平均分群法硬體架構，一個軟硬體共同設計之相片檢索系統，以及兩個支援特徵截取以及機器學習演算法之高效能單晶片系統，作為多媒體分析系統運算的一系列解決方案。 | zh_TW |
| dc.description.abstract | Nowadays, thanks to the development of semiconductor technology, there are more and more versatile applications in Consumer Electronics (CE) products. Different kinds of CE products, such as cellular phones, digital still cameras, portable computers, are gradually integrated into one single system. In the near future, a CE product might include different functionalities, including making phone calls, sending e-mail, and taking/storing photos. At the same time, the advance of memory is also astonishing. The size of flash memory is increasing, but its price is decreasing steadily. Obviously, the new memory technology might replace the traditional hard disk for data storage. Because of the development of the Internet and the large storage of data, managing multimedia content becomes an important and indispensable task. Therefore, the integration with different kinds of functionalities and the increase of multimedia data result in the necessity of automatic multimedia content analysis for CE products. In embedded systems for CE products, the traditional CPU/RISC and ASIC cannot satisfy both the flexibility and performance requirements of multimedia applications based on their architectures, so the exploration of new design methodologies and solutions are needed for next-generation applications.
In this dissertation, new implementation methods and frameworks of multimedia content analysis are proposed. From algorithm designs, architectural analyses, hardware architectural designs, software/hardware co-designs, and SoC designs, a systematic approach is adopted. The proposed methods provide a series of new solutions to next-generation applications for consumer electronics (e.g. mobile devices). To effectively analyze the contents of multimedia, feature extraction and machine learning algorithms are both indispensable. There are lots of machine learning algorithms that are widely employed in different applications, and they can be regarded as essential components or building blocks for multimedia content analysis. To handle the supervised learning and unsupervised learning algorithms in machine learning, both high-performance hardware architectures and reconfigurable hardware architectures are proposed. For high-performance architectures, K-Means clustering algorithm is the focus in this dissertation because of its popularity and importance, and its applications are also demonstrated. A total of four kinds of K-Means architectures are developed. For reconfigurable hardware architectures, two System-on-a-Chip (SoC) architectures with different features are proposed. These systems can process a large amount of data in parallel and perform feature extraction with high bandwidth, and they can also deal with various kinds of machine learning algorithms, such as K-Means clustering, K-Nearest Neighbor classification, Gaussian Mixture Model-based classification, Support Vector Machine, and Artificial Neural Network. In short, the contribution of this dissertation consists essentially of two algorithms for video and image segmentation, one software/hardware co-design platform, four different kinds of architectures for K-Means clustering, and two SoCs for multimedia content analysis. The content of this dissertation can also be regarded as a series of new solutions to multimedia content analysis for CE products. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T07:08:22Z (GMT). No. of bitstreams: 1 ntu-99-F95943020-1.pdf: 4413071 bytes, checksum: 01a1ada1c8f00a7a5cf93b12e370f617 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Abstract xix
1 Introduction 1 1.1 Multimedia Content Analysis . . . . . . . . . . . . . . . . . . . . 2 1.2 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.1 Feature Extraction . . . . . . . . . . . . . . . . . . . . . 4 1.2.2 Machine Learning . . . . . . . . . . . . . . . . . . . . . 5 1.3 System Architectures . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 Stream Processor . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 Reconfigurable Hardware . . . . . . . . . . . . . . . . . 7 1.3.3 Design Challenges . . . . . . . . . . . . . . . . . . . . . 8 1.4 Research Contributions and Dissertation Organization . . . . . . . 10 1.4.1 Algorithm Design . . . . . . . . . . . . . . . . . . . . . 10 1.4.2 Architectural Analysis and Design . . . . . . . . . . . . . 11 1.4.3 Software/Hardware Co-Design . . . . . . . . . . . . . . . 12 1.4.4 SoC Design . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Algorithm Design: Video Object Segmentation Based on K-Means Background Clustering and Watersheds 17 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Proposed Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 Background Modeling . . . . . . . . . . . . . . . . . . . 18 2.2.2 Object Mask Generation . . . . . . . . . . . . . . . . . . 22 2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 Algorithm Design: Fast Image Segmentation and Texture Feature Extraction for Image Retrieval 31 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Proposed Image Segmentation Method . . . . . . . . . . . . . . . 34 3.2.1 Color Space Transform and Histogram Generation . . . . 34 3.2.2 Maximin Initialization and Parameter Estimation . . . . . 38 3.2.3 K-Means Clustering in HSV Color Space . . . . . . . . . 38 3.2.4 Post-Processing of Spatial Regions . . . . . . . . . . . . 42 3.3 Proposed Texture Feature Extraction Technique . . . . . . . . . . 42 3.3.1 Texture Feature based on Discrete Wavelet Transform . . 44 3.3.2 Proposed Technique based on Label Wavelet Transform . 45 3.3.3 Retrieving Process . . . . . . . . . . . . . . . . . . . . . 47 3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4.1 Fast Color Image Segmentation . . . . . . . . . . . . . . 48 3.4.2 Efficient Texture Feature Extraction . . . . . . . . . . . . 50 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 Architectural Analyses of K-Means Silicon Intellectual Property for Image Segmentation 59 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.1 K-Means Algorithm . . . . . . . . . . . . . . . . . . . . 61 4.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . 63 4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 Architectural Design: Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis 73 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 K-Means Algorithm and Hardware Considerations . . . . . . . . 75 5.3 Proposed Hardware Architecture . . . . . . . . . . . . . . . . . . 81 5.3.1 Control Unit and Pseudo Random Number Generator . . . 82 5.3.2 Parallel E-M Distance Calculator Set . . . . . . . . . . . 84 5.3.3 8-Layer Parallel M-S PE Set . . . . . . . . . . . . . . . . 85 5.3.4 Summation Updating Engine . . . . . . . . . . . . . . . . 86 5.3.5 Vector Divider . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.6 Convergence Monitor and Labeling Engine . . . . . . . . 93 5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6 Architectural Design: Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number 101 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 Hierarchical K-Means (HK-Means) Algorithm. . . . . . . . . . . 103 6.3 Hardware Architecture Overview . . . . . . . . . . . . . . . . . . 108 6.4 Hierarchical Memory . . . . . . . . . . . . . . . . . . . . . . . . 111 6.4.1 Memory Cost Analysis . . . . . . . . . . . . . . . . . . . 111 6.4.2 Memory Architecture . . . . . . . . . . . . . . . . . . . . 114 6.5 Data Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.5.1 Traverse Processing Element (Traverse PE) . . . . . . . . 118 6.5.2 Centroid Visiting in Binary Tree . . . . . . . . . . . . . . 120 6.6 Iteration Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 123 6.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7 Software/Hardware Co-Design: Photo Retrieval based on Spatial Layout with Hardware Acceleration 131 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2 Proposed Photo Retrieval System . . . . . . . . . . . . . . . . . . 135 7.2.1 Image Segmentation . . . . . . . . . . . . . . . . . . . . 137 7.2.2 Feature Extraction . . . . . . . . . . . . . . . . . . . . . 139 7.2.3 Image Matching . . . . . . . . . . . . . . . . . . . . . . 142 7.2.4 Ranking . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.3 Proposed K-Means Accelerator . . . . . . . . . . . . . . . . . . . 144 7.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.3.2 Characteristics and Applications . . . . . . . . . . . . . . 152 7.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 153 7.4.1 Photo Retrieval Algorithm . . . . . . . . . . . . . . . . . 153 7.4.2 Robustness Evaluation . . . . . . . . . . . . . . . . . . . 159 7.4.3 K-Means Hardware Accelerator . . . . . . . . . . . . . . 163 7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 8 SoC Design: Tera-scale Performance Machine Learning SoC (MLSoC) with Dual Stream Processor Architecture for Multimedia Content Analysis 167 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 8.2 Machine Learning SoC (MLSoC) Architecture . . . . . . . . . . 169 8.3 Image Stream Processor . . . . . . . . . . . . . . . . . . . . . . 171 8.3.1 Linear Processor . . . . . . . . . . . . . . . . . . . . . . 175 8.3.2 Order Processor . . . . . . . . . . . . . . . . . . . . . . . 177 8.4 Feature Stream Processor . . . . . . . . . . . . . . . . . . . . . . 178 8.5 VLSI Implementation . . . . . . . . . . . . . . . . . . . . . . . . 181 8.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 8.7 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . 186 9 SoC Design: Multimedia Semantic Analysis SoC (SASoC) with Machine-Learning Engine 187 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 9.2 System Architecture Design . . . . . . . . . . . . . . . . . . . . 192 9.2.1 Image Stream Processing System (ISPS) . . . . . . . . . 192 9.2.2 Feature Stream Processing System (FSPS) . . . . . . . . 194 9.2.3 Example Applications . . . . . . . . . . . . . . . . . . . 197 9.3 Chip Design Flow and Verification Strategies . . . . . . . . . . . 198 9.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 200 9.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 9.6 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . 206 10 Conclusions and Future Directions 209 10.1 Principal Contributions . . . . . . . . . . . . . . . . . . . . . . . 209 10.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.2.1 New Algorithms for Multimedia Content Analysis . . . . 211 10.2.2 New System Architectures for Machine Learning Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Reference 213 | |
| dc.language.iso | en | |
| dc.subject | 機器學習 | zh_TW |
| dc.subject | 數位電路 | zh_TW |
| dc.subject | 多媒體內容分析 | zh_TW |
| dc.subject | 硬體架構 | zh_TW |
| dc.subject | digital circuit | en |
| dc.subject | machine learning | en |
| dc.subject | hardware architecture | en |
| dc.subject | multimedia content analysis | en |
| dc.title | 多媒體內容分析系統之演算法與積體電路架構設計 | zh_TW |
| dc.title | Algorithm and VLSI Architecture Design of Multimedia Content Analysis System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 陳良基(Liang-Gee Chen),徐宏民(Winston H. Hsu),傅楸善(Chiou-Shann Fuh),杭學鳴(Hsueh-Ming Hang),賴尚宏(Shang-Hong Lai),張添烜(Tian-Sheuan Chang),廖弘源(Hong-Yuan Mark Liao) | |
| dc.subject.keyword | 數位電路,多媒體內容分析,硬體架構,機器學習, | zh_TW |
| dc.subject.keyword | digital circuit,multimedia content analysis,hardware architecture,machine learning, | en |
| dc.relation.page | 229 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-11-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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