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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48042完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Yi-Chun Hsieh | en |
| dc.contributor.author | 謝依峻 | zh_TW |
| dc.date.accessioned | 2021-06-15T06:45:00Z | - |
| dc.date.available | 2012-08-22 | |
| dc.date.copyright | 2011-08-22 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-20 | |
| dc.identifier.citation | [1] B.G. Lee and R.M. Tsang, “A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-gm Opamp,” IEEE J. Solid-State Circuits, vol.44, pp. 883, Mar. 2009.
[2] N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, and U. Moon, 'A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback,' IEEE J. Solid-State Circuits,vol.44,pp 2392,Sep.2009 [3] B.G Lee, B.M. Min, G. Manganaro, and J.W. Valvano, ”A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb 2008, pp. 224-225 [4] P. Y. Wu, V. S. L. Cheung, and H. C. Luong, “A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture,” IEEE J. Solid-State Circuits,vol. 42, pp. 730-738, Apr. 2007 [5] S.H. Lewis and H.S. Fetterman, 'A 10-b 20-Msample/s analog-to-digital converter,' IEEE J. Solid-State Circuits, vol.27, no.3, pp.351-358, Mar 1992 [6] D.W. Cline and P.R. Gray, 'A power optimized 13-b 5M samples/s pipelined analog-to-digital converter in 1.2μm CMOS,' IEEE J. Solid-State Circuits, vol.31, no.3, pp.294-303, Mar 1996 [7] K. Nagaraj, H.S. Fetterman, J. Anidjar, S.H. Lewis, and R.G. Renninger, 'A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,' IEEE J. Solid-State Circuits, vol.32, no.3, pp.312-320, Mar 1997 [8] B.Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [9] S.C. Lee, Y.-D. Jeon, J.K. Kwon, and J. Kim, “A 10-bit 205-MS/s 1.0- mm 90-nm CMOS pipeline ADC for flat panel display applications,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2688–2695,Dec. 2007. [10] A.M. Abo, and P.R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to- digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999. [11] M. Miyahara, and A. Matsuzawa, “A 10b 320 MS/s 40 mW Open-Loop Interpolated Pipeline ADC,” IEEE Symp. VLSI Circuits, pp. 126-127, Jun. 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48042 | - |
| dc.description.abstract | 在高速、中高解析度類比數位轉換器中，導管式的類比數位轉換器是最常使用一種方式。為了減低功率消耗，許多作品[1], [2], [3], [4]使用電容分享技術。傳統的電容分享技術使用了放電相位來取消回授電容上的電荷。但是放電相位占據放大相位的時間，使得功率消耗上升。此外，傳統的電容分享技術只有使用在第一級。這本作品，放電相位被移除，並且電容分享技術使用在第一級與第二級，所以功率消耗更進一步的減少。
一個1.2V電壓，以90nm的類比數位轉換器在取樣頻率為200MS/s，輸入頻率為1.99MHz的情況下，SNDR為53.14dB。 MOS製程實現的一個每秒兩億次的導管式類比數位轉換器被提出來。在取樣頻率為200MS/s，輸入頻率為99MHz的情況下，SNDR為50.25dB，INL，DNL分別為+1.59/-1.91 LSB，+0.70/-0.75 LSB,。操作在電源電壓為1.2V時，功率消耗為45.4mW。類比數位轉換器所占的面積為0.53 mm2. | zh_TW |
| dc.description.abstract | In high speed, medium-high resolution analog-to-digital converter (ADC), the pipelined architecture is the most common used. To reduce the power consumption, the capacitor-sharing technique is used in [1], [2], [3], [4]. Conventional capacitor-sharing technique employed the discharge phase to cancel the charge on feedback capacitor. However, the discharge phase occupied the amplification phase, and power consumption is raised. In additional, conventional capacitor-sharing technique is also only applied in first stage. In proposed work, the discharge phase is removed, and capacitor-sharing technique is applied to first and second stage; hence the power consumption is further reduced.
A 10-bit pipelined ADC with 1.2V, 200MS/s, in 90nm technology is proposed. In 200MS/s with 1.99MHz input, the signal to noise and distortion ratio is 53.14dB. In 200MS/s with 99.9MHz input, the SNDR is 50.25dB. Integral Nonlinearity and differential nonlinearity are +1.59/-1.91 LSB and +0.70/-0.75 LSB respectively. The power consumption is 45.4mW at 1.2V power supply. The ADC occupies an active area of 0.53 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T06:45:00Z (GMT). No. of bitstreams: 1 ntu-100-R97943131-1.pdf: 1809852 bytes, checksum: 48a93adb071855c9f26064c55f13aab2 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | CONTENTS
誌謝 I 摘要 II ABSTRACT III CONTENTS IV LIST OF FIGURES VII LIST OF TABLES X Chapter 1 Introduction 1 1.1 Motivation and design goal 1 1.2 Thesis organization 2 Chapter 2 Fundamental of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 ADC Performance Metrics 3 2.2.1 Static Performance 3 2.2.2 Dynamic Performance 5 2.3 Pipelined ADC Architecture 8 2.3.1 1.5bit-perStage Architecture 9 2.3.2 Pipelined ADC Accuracy Requirement 12 Chapter 3 Proposed Capacitor-Sharing Technique for Pipelined ADC 15 3.1 Introduction 15 3.2 Typical Capacitor Sharing techniques 19 3.2.1 Prior Work 1: Two Set of CF to Realize β of 1/2 19 3.2.2 Prior Work 2: Extra Capacitor to Avoid Memory of CF 21 3.2.3 Prior Work 3: Extra Discharge Phase to Avoid Memory of CF 23 3.3 Proposed Capacitor-Sharing Technique 25 3.3.1 Proposed Topology 1: Charge Neutralization on MDAC 1 and 2 25 3.3.2 Proposed Topology 2: Capacitor-Sharing applied on MDAC 2 and 3 27 3.3.3 Comparison with Prior Works [1], [2], [4] 29 3.4 Proposed Architecture 32 3.4.1 Schematic of First Three Stage 33 3.4.2 2-bit Front-end to Reduce Opamp Swing Requirement 34 3.4.3 Error Analysis of Charge Neutralization 36 Chapter 4 Circuit Implementation and Simulation Results 38 4.1 Introduction 38 4.2 Circuit Implementation 38 4.2.1 Opamp 38 4.2.2 Clock Generator 47 4.2.3 Comparator 49 4.2.4 Bootstrap Circuit 50 4.3 Simulation Result 51 4.3.1 Opamp 51 4.3.2 INL and DNL Analysis 52 4.3.3 FFT Simulation 52 4.4 Summary 54 Chapter 5 Test Setup and Measurement Results 55 5.1 Introduction 55 5.2 Test Setup 55 5.3 PCB Design 56 5.4 Experimental Result 60 5.4.1 Static Linearity 60 5.4.2 Dynamic Performance 62 5.5 Summary 64 Chapter 6 Conclusion and future work 67 6.1 Conclusions 67 6.2 Future work 67 Bibliography 69 | |
| dc.language.iso | en | |
| dc.title | 一個低功率每秒兩億次取樣，十位元之管線式類比數位轉換器 | zh_TW |
| dc.title | A Low Power 200MS/s, 10bit Pipelined Analog to Digital Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 導管式類比數位轉換器,低功率,高速, | zh_TW |
| dc.subject.keyword | pipelined ADC,low-power,high-speed, | en |
| dc.relation.page | 70 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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