利用可滿足性基礎的克萊格內插法增大栓鎖時脈之函數

Abstract

現今低功率消耗電路設計中節省動態功率消耗越來越受到重視，節省動態功率消耗最有效的技術之一是時脈閘控(Clock Gating)，該技術阻擋那些不需要的時脈切換活動以達到節省動態功率消耗的目的。在這篇論文中，我們應用內插技術(Interpolation)在可滿足性基礎的時脈閘控演算法中給予增大原演算法求得之時脈閘控函數的靈活性。我們還開發了多種技術來改良時脈閘控演算法所需的時間花費與記憶體使用量，其中包含了一個根據時脈閘控函數能力的篩選器以減少可滿足性時脈閘控演算法中所需要的正規滿足性驗證的次數。一個可滿足性解法器中動態返回次數限制機制以縮短可滿足性解法器在驗證時脈閘控函數所需的驗證時間。此外，一個縮減時脈閘控函數邏輯閘的方法來減輕因增加時脈閘控邏輯閘所造成的面積花費。實驗結果顯示我們所提出的演算法在增加百分之五的面積花費中條件下能有阻擋兩倍於現今可靠性基礎的時脈閘控演算法中不需要的時脈切換活動。

Dynamic power saving is gaining its dominance in modern low power designs, while clock gating, which blocks unnecessary clock switching activities, is one of the most efficient approaches to reduce the dynamic power. In this thesis, we exploit the interpolation technique in a SAT-based clock gating algorithm in order to grant a greater flexibility in enlarging the gating capabilities over the original gating candidates. We also developed several techniques to improve the runtime and memory usage of the clock gating algorithm, including a gating capability filter to reduce the number of formal SAT proofs, a dynamic backtracking limit controller to shorten the SAT runs, and a shrinking method to ease the final gate count overhead. The experimental results show that our proposed algorithm can gate up to 2X clock switches with less than 5% area overhead when compared to the state-of-the-art SAT-based clock gating methodology.