適用於光池加速光線追蹤繪圖之多核心處理器硬體架構設計

Abstract

逼真的電腦繪圖技術如今已是日常生活中的一部份。但人們依舊追求更高端更真實的繪圖技術，傳統的柵格化投影技術已不再能滿足此需求。光線追蹤等物理擬真新渲染技術被看好具備十足的潛力，但仍有技術問題尚待克服：高運算量與高動態分歧。本篇論文提出一種新的光線追蹤加速硬體架構，期待克服以上問題，進而涉足即時光線追蹤渲染的境界。 光線追蹤相較傳統做法多了光線生成、空間追蹤、交點測試等運算步驟。其中，每次光線可能出現偏折散射時，會指數增長出更多需要追蹤的新目標；甚至更細膩的繪圖上還需要大量取樣機率分布，如：路徑追蹤演算法。更甚者，這些光線還要與數十萬的三角形物件進行交點測試，進而開啟了加速結構的研究大門。此外，這些目標光線隨空間的行進將越來越發散，難以用現今的通用圖形處理器來平行加速。每次偏折都帶來運算上的分歧，使得快取記憶在讀取上失去區域性的好處，拖慢了整體的速度。 本論文所提出了「光池加速光線追蹤繪圖器」的新硬體加速架構，以克服這些問題。本架構亦參考相關的先前文獻如SGRT、PowerVR GR6500等，將整個運算過程分為兩部分：專責空間追蹤和交點測試的硬體追蹤單元，以及保留了可程式化能力的渲染器單元。本文的光池加速架構希望能透過介於其間的兩個光池，重分配調和上述兩運算單元的工作，進而達到高效率運算的好處。藉由光池的重整與抽象化，運算單元將可更獨立，各自進行所需的高速運算。 其中，本論文針對渲染運算單元，設計了一個參數化且易於重組的多核心處理器。其特色在於：把運算分組為功能單元，各功能單元都能輕易的在此處理器的設計上添減、方便擴充與客製化所需的功能。此處理器經邏輯合成驗證，在TSMC 40奈米製程下能以1GHz的時頻運作，並附帶一個近乎時間精確的軟體模擬器供開發測試。 經模擬實驗，此一光池加速光線追蹤繪圖器可以達到每秒處理一億條光線(100Mrays/s)的最高效能。該系統包含四組運算單元(每組含8核心8套資料)、108千位元組(KB)的光池與特化硬體追蹤單元(具每秒一億筆空間追蹤能力)。此一系統得以即時渲染基本光線(primary ray only)於高畫質(HD, 720p)解析度上，或是即時渲染五層懷式演算法反射光於傳統解析度(480p)上。

Realistic image synthesis is now everywhere in our daily lives. People pursue new ex-perience of much more realistic of displays than traditional rasterization-based method. Ray tracing, as one of the physically-based rendering methods, is provided as a candi-date for next generation of image synthesis. However, it comes with problems about large scale computation and diversity to be conquered. In this thesis, a simple but com-plete hardware for real time ray tracing is proposed, trying to overcome these problem. Ray tracing requires additional computation of ray generation, traversal and inter-section test with objects. These rays may grow exponentially as each bounce of reflec-tion and refraction or even samples of specific distribution for path tracing. Meanwhile, there are hundreds of thousands of triangles to test. It starts the researches of acceler-ating data structures for them. On the other side, rays become more and more diverse as they traverse deeper. It is not compatible to the programming model of current GPGPUs. The divergence of data access in ray tracing causes the performance drop by cache evictions. Ray-pool based ray tracer (in short as RPRT) is then proposed. As a hardware ar-chitecture to solve these problem. Like previous work such as SGRT and PowerVR GR6500, RPRT separates the process of traversal and intersection to a specialized hardware while keeping the programmability in shader. RPRT tries to make these two computational units co-works efficiently by adding two pool between them. By the arrangement and virtualization of two pools, the two computational unit can work sim-ultaneously and independently. In this system, a configurable multiprocessor is designed as the need for shader. It is easy to configure and easy to extend for different applications with customized ALUs. It comes with a near cycle accurate simulator verified by hardware implementa-tion after logic synthesis. It works at the clock rate of 1GHz under the TSMC 40 nm process. By experiments on RPRT system, it can reaches 100Mrays/s of performance under the configuration of 4 compute units multiprocessor, 8 warps 8 cores in each CU, 108KB pools, and an ASIC traverser with ability of about 100Mtraversal/s. This result reveals the possibility of real-time hardware ray tracing at 720p with basic effects by primary rays and 480p by the traversal depth of 5.