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標題: | 毫米波段注入式鎖定除頻器 Millimeter-Wave Injection-Locked Frequency Dividers |
作者: | Chiao-Hsing Wang 王巧星 |
指導教授: | 劉深淵(Shen-Iuan Liu) |
關鍵字: | 毫米波,注入式鎖定除頻器,除2,除3,除4, Millimeter-Wave,Injection-Locked Frequency Divider,ILFD,Divide-by-2,Divide-by-3,Divide-by-4, |
出版年 : | 2010 |
學位: | 碩士 |
摘要: | 隨著現代CMOS製程技術的發展與進步,以往必需使用BJT來實現的高速電路將被CMOS取代。驅使了許多毫米波段的應用,例如: 點對點的通訊,影像感測器,車用雷達系統,電波相關天文學。在上述的應用中,用在震盪器或者通道選擇器時,鎖相迴路(PLL)是一個關鍵的構成元件
為了實現非常高速PLL,位於VCO後第一級的除頻器將是一個關件組件。它必須有很高的操作頻率,大的鎖定範圍和低功率的消耗。在毫米波電路的設計,被動電感,耦合電容和電晶體的寄生電容將會減少電路的操作頻率。利用電感和電容為震盪器基礎的注入式鎖定除頻器(ILFDs),可以提供好的方法去解決高操作頻率,低功率消耗和低相位雜訊。但是,ILFDs的鎖定範圍相常地被受限。因此,利用π形狀的電感和電容震盪腔增加了一個H-band(220-325GHz)的除2 ILFD的可操作的頻率。它的鎖定範圍,操作頻率和設計考量將在第3章分析。因為避免了串接式的除頻器階層,所以有著高除數的ILFD可以減少直流功率的消耗和減少晶片的面積利於將更加複雜的電路的積體化。三個D-band(110~170GHz)除3的ILFDs和二個除4的ILFDs,對於增加它們鎖定範圍的電路技巧將分別在第4章和第5章呈現。 With the development and progress of CMOS process, the high-speed circuits should be realized by BJT in the past are gradually replaced by CMOS. It inspires many millimeter-wave applications; such as point to point communications, image sensing, automotive radar systems, radio astronomy. Using in above applications, the phase-locked loop (PLL) is an important component to sever as a local oscillator or channel selector. To realize a very-high-speed PLL, the frequency divider following the VCO will be a crucial building block. It must have high operation frequency, wide locking range, and low power consumption. In millimeter wave circuits design, the parasitic capacitances of passive inductors, coupling capacitors and transistors will decrease the operation frequency of circuits. Injection-locked frequency dividers (ILFDs) with LC tank based oscillators can be a good solution for high operation frequency, low power consumption and low phase noise. However, their locking ranges are quite limited. Therefore, a proposed H-band (220-325GHz) divide-by-2 ILFD enhances the operation frequency by using the π-type LC tank. The locking range and operation frequency, and the design considerations are analyzed in chapter 3. ILFDs with high division ratio will reduce dc power and chip area for compact integration since the cascaded divider stages are avoided. Three D-band (110~170GHz) divide-by-3 ILFDs and divide-by-4 ILFDs with locking range enhancement techniques are presented in chapter 4 and chapter 5, respectively. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47723 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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