請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47311完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 盧奕璋 | |
| dc.contributor.author | Wei-Cheng Hsieh | en |
| dc.contributor.author | 謝為丞 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:54:32Z | - |
| dc.date.available | 2013-08-20 | |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-17 | |
| dc.identifier.citation | [1] B. Razavi, “Principles of Data Conversion System Design,” NJ: IEEE PRESS, 1995.
[2] J. L. McCreary, and P. R. Gray, “ All-MOS charge redistribution analog-to-digital conversion techniques-Part I, ” IEEE Journal of Solid-State Circuits (JSSC), vol. SC-10, pp. 371-379, Dec. 1975. [3] A. M. Abo, and P. R. Gray, “ A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter , ” IEEE Journal of Solid-State Circuits (JSSC), vol. 34, no. 5, pp. 599-606, May. 1999. [4] A. Rossi, and G. Fucili, “ Nonredundant successive approximation register for A/D converters, ” Electron. Letters, vol. 32, no. 12, pp. 1055-1057, Jun. 1996. [5] M. D. Scott, B. E. Boser, and K. S. J. Pister, “ An ultralow-energy ADC for smart dust, ” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 7, pp. 1123-1129, Jul. 2003. [6] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “ A 0.5-V 1-uW successive approximation ADC, ” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 7, pp. 1261-1265, Jul. 2003. [7] N. Verma, and A. P. Chandrakasan, “ A 25uW, 100KS/s 12b ADC for wireless micro-sensor applications, ” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp.222-223, Feb. 2006 [8] S.-W. Michael Chen, and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2669–2680, Dec. 2006. [9] J. Graninckx, and G. Van der Plas, “ A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS, ” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp.246-247. Feb. 2007 [10] B. P. Ginsburg, and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 4, pp. 739–747, Apr. 2007. [11] H.-C. Hong, and G.-M. Lee “A 65-fJ/conversion-step 0.9-V 200-KS/s rail-to-rail 8-bit successive approximation ADC,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 10, pp. 2161-2168, Oct. 2007. [12] Y.-K. Chang, C.-S. Wang, and C.-K. Wang “A 8-bit 500KS/s low power SAR ADC for bio-medical application,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 228-231, Nov. 2007. [13] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx “An 820µW 9b 40MS/s noise-tolerant dynamic SAR ADC in 90nm digital CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 238-239, Feb.2008 [14] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “ A 9.4ENOB 1V 3.8uW 100KS/s SAR ADC with timedomain comparator, ” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp.246-247, Feb. 2008. [15] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9µW 4.4fJ/conversion-step 10b 1MSs charge redistributed ADC,” IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 244-245, Feb.2008 [16] A. Agnes, E. Bonizzoni, and F. Maloberti, “ Design of an ultra-low power SA-ADC with medium/high resolution and speed,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3049-3052, May 2008. [17] J. He, S. Zhan, D. Chen, and R. L. Geiger, “ Analyses of static and dynamic random offset voltages in dynamic comparators, ” IEEE Transaction on Circuits and Systems-I (TCAS-I), Reg. Papers, vol. 56, no. 5, pp. 911-919, May 2009. [18] Y. Chen, S. Tsukamoto, and T. Kuroda “Split capacitor DAC mismatch calibration in successive approximation ADC,” IEEE Custom Integrated Circuits Conference (CICC), pp. 279-282, Sep. 2009. [19] Y. Chen, S. Tsukamoto, and T. Kuroda “A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 145-148, Nov. 2009. [20] H.-W. Chen, Y.-H Liu, Y.-H. Lin, and H.-S. Chen “A 3mW 12b sub-range SAR ADC,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 153-156, Nov. 2009. [21] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC,”IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 388-389, Feb. 2010. [22] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “ A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, ” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 731-740, Apr. 2010. [23] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P U, R. P. Martins, and F. Maloberti, “ A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS, ” IEEE Journal of Solid-State Circuits (JSSC), vol. 45, no. 6, pp. 1111-1121, Jun. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47311 | - |
| dc.description.abstract | 本論文完整分析了在連續漸進式類比數位轉換器在不同的電容陣列架構下，其所需消耗的切換能量。依據不同的耗能設計需求，提供三種主要的電容陣列架構給設計者，分別為傳統式、跨接式和C-2C式的架構。 提出的電容陣列架構，在10位元解析的規格下比對於跨接式和傳統式架構，分別省了25.39%以及95.7%的切換能量。使用此新穎的電容陣列設計出一個具有10位元解析度、每秒100萬次取樣速度且適用於生醫應用的單端連續漸進式類比數位轉換器。以TSMC 90奈米製程進行模擬，其結果顯示功率損耗僅為3.43微瓦、在達到Nyquist頻率的有效解析度為9.65位元，FOM低達平均每次步階轉換5.1f焦耳。 | zh_TW |
| dc.description.abstract | In this thesis, the complete analysis of switching energy in different types of capacitor array of SAR ADCs has been derived. The 3 main types of capacitor array, conventional, attenuation, and C-2C structures are recommended to designers who have different requirements of power budgets. The proposed capacitor array saves 25.39% of switching energy compared to the attenuation structure and 95.7% compared to the conventional structure in 10bit resolution cases. A 10bit, 1MS/s single-ended SAR ADC with the novel capacitor array is designed for bio-medical applications. Simulation results of the proposed ADC show the average power is 3.43 W and the ENOB reaches 9.65 bits within the Nyquist rate. The FOM is as low as 5.1fJ/conversion-step using the TSMC 90nm process. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:54:32Z (GMT). No. of bitstreams: 1 ntu-99-R96943125-1.pdf: 1237606 bytes, checksum: 1162337e5cb5422c22a0d6136db24ed8 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 3 中文摘要 5 Abstract 6 Contents 7 List of Figures 10 List of Tables 12 Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 ADC and Quantization Noise 3 2.2 Static Performance Metrics 5 2.2.1 Differential Nonlinearity (DNL) 6 2.2.2 Integral Nonlinearity (INL) 6 2.2.3 Offset Error 7 2.2.4 Gain Error 7 2.3 Dynamic Performance Metrics 7 2.3.1 Signal-to-Noise Ratio (SNR) 7 2.3.2 Total Harmonic Distortion (THD) 8 2.3.3 Spurious Free Dynamic Range (SFDR) 8 2.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 9 2.3.5 Effective Number of Bits (ENOB) 9 2.3.6 Effective Resolution Bandwidth (ERBW) 9 2.4 Summary 9 Chapter 3 Analysis of Switching Sequence in SAR ADC 10 3.1 Introduction 10 3.2 Energy-Efficient Procedure for Capacitor Array 12 3.2.1 Splitting Technique and Energy-Saving Sequence 12 3.2.2 Attenuation Capacitor Array 15 3.2.3 Proposed Energy-Efficient Capacitor Array 23 3.2.4 Capacitor Mismatch Considerations 25 3.2.5 kT/C Noise Considerations 27 3.2.6 Summary 28 3.3 Design Guideline of Capacitor Array 30 Chapter 4 Design of a 10-bit 1-MS/s 30fJ/c.-s. ADC 33 4.1 ADC Architecture and Operation Illustration 33 4.2 Sampling Switches 35 4.2.1 Complementary Switch 35 4.2.2 Constant-Vgs Booster and Track-and-Hold (T/H) Circuit 36 4.2.3 Supply-dpendent Booster 38 4.2.4 Switch for Capacitor Array 39 4.3 Dynamic Comparator 41 4.3.1 Offset Considerations 43 4.3.2 Rail-to-rail Input Capability 44 4.4 Successive Approximation Register (SAR) 46 4.4.1 SAR 46 4.4.2 Energy-efficient Logic Block 48 4.5 Layout Floorplan 49 4.5.1 Capacitor Array Floorplan 49 4.5.2 Comparator Floorplan 50 4.5.3 SAR ADC Floorplan 51 4.6 Simulation Results 53 4.6.1 FFT Simulation Results 53 4.6.2 Power Distribution 56 4.6.3 Figure of Merit (FOM) 57 Chapter 5 Measrement Results 59 5.1 PCB Design 59 5.2 Measurement Setup 60 5.3 Measurement Performance 61 Chapter 6 Conclusion and Future Works 62 6.1 Conclusion 62 6.2 Future Works 62 Bibliography 64 | |
| dc.language.iso | en | |
| dc.subject | 切換邏輯 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | low power | en |
| dc.subject | SAR | en |
| dc.subject | switching sequence | en |
| dc.subject | ADC | en |
| dc.title | 連續漸進式類比數位轉換器之節能分析與設計 | zh_TW |
| dc.title | nalysis and Design of Low Power SAR ADCs | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成,林宗賢,陳信樹 | |
| dc.subject.keyword | 低功率,切換邏輯,連續漸進式,類比數位轉換器, | zh_TW |
| dc.subject.keyword | low power,switching sequence,SAR,ADC, | en |
| dc.relation.page | 67 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-99-1.pdf 未授權公開取用 | 1.21 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。