以現場可程式化類比陣列實現三角積分調變器漏電流之量測

Abstract

本篇論文實現一個量測三角積分調變器中的積分器漏電流的方法。利用現場可程式化類比陣列來實現三角積分調變器的硬體架構，使用一個直流電壓做為測試信號。對三角積分調變器中的積分器進行充放電，記錄放電時間並且據此來分析出積分器的漏電流現象。整個測試方法分為三個階段。在第一階段中利用一個定電壓的直流信號對積分器進行充電，使積分器達到穩定而不超過飽和上限的電壓值。然後在第二階段時使積分器放電同時記錄放電時間，並且根據放電時間推算出積分器的漏電率。在第三階段中，則決定是否重新進行一次新的量測以增進量測的準確率。 現場可程式化類比陣列主要由四個可組態類比區塊所組成，每一個區塊都有運算放大器、比較器、電容陣列等基本元件。利用切換式電容技術透過這些元件的組合來設計各種類比電路。使用現場可程式化類比陣列可以快速而且動態地進行電路設計，大幅節省設計時間與成本。 本論文利用現場可程式化類比陣列設計一個可調整漏電率的三角積分調變器，並且利用這個電路來實現上述漏電流量測方法。使用資料擷取模組來產生測試信號及擷取現場可程式化類比陣列的輸出信號以進行分析，最後則根據實驗結果提出一個簡單的改進量測準確率方法，比較改良前後的量測結果，最大量測誤差由1.89%改進為1.17%。

In this thesis, we implement a Design-for-Test (DfT) technique to measure the integrator leakage of ΔΣ modulator. We use Field Programmable Analog Array (FPAA) to implement the ΔΣ modulator and utilize DC voltage as the test stimulus. The integrator leakage testing method is base on integrator charging/discharging; it is an iterative three-phase approach. In phase I, the integrator is charged with a constant DC input to reach a stable, leakage-dependent voltage level. In phase II, the integrator is gradually discharged. The time of discharging is recorded and used to derive the integrator leakage. In phase III, it is determined whether a new iteration can be executed to further enhance the test accuracy. The field programmable analog array device is based on the switched capacitor technology. It is composed of four configurable analog blocks, seven IO cells, a clock generator, and configuration interface. The basic configurable analog block is composed of two operational amplifiers, a comparator and eight capacitor arrays. Circuits are realized through manipulation of switches between various circuit components inside the configurable analog block. Using field programmable analog array to design circuit will save us a lot of time and money. We use the field programmable analog array to design a ΔΣ modulator with tunable integrator leakage and utilize DAQ to generate the test signal and acquire the output signal from FPAA. According to the experimental result, we improve the test method to achieve better accuracy --- the maximum error is reduced from 1.89% to 1.17%.