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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Tang-Lam Wong | en |
dc.contributor.author | 王登霖 | zh_TW |
dc.date.accessioned | 2021-06-15T05:47:47Z | - |
dc.date.available | 2016-09-18 | |
dc.date.copyright | 2011-09-18 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-08-29 | |
dc.identifier.citation | [1] Behzad Razavi, “Design of Integrated Circuits for Optical Communications”, McGRAW-Hill,2003.
[2] A. X. Widmer and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM J. Res. And Develop., vol. 27, pp. 440-451, Sept. 1983. [3] “10 Gigabit Ethernet Technology Overview White Papers,” Revision 1.0, 10 Gigabit Ethernet Alliance, May 2001 [4] D. Belot, L. Dugoujon and S. Dedieu, “A 3.3V Power Adaptive 1244/622/155Mbit/s Transceiver for ATM, SONET/SDH”, IEEE Journal of Solid-State Circuits, vol.33, no.7, pp. 1047-1058, July 1998. [5] J. Scheytt, G. Hanke and U. Langman, “A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems”, IEEE Journal of Solid-State Circuits, vol.34, no.12, pp. 1935-1943, Dec. 1999. [6] J. Frambach, R. Heijna and R. Krosschell, “Single Reference Continuous Rate Clock and Data Recovery from 30Mbit/s to 3.2Gbit/s”, IEEE Custom Integrated Circuits Conference, pp.375-378, 2002. [7] Declan Dalton, Kwet Chai, Eric Evans, Lawrence DeVito and etc. “A 12.5-mb-s to 2.7-Gb-s Continuous-rate CDR with Automatic Frequency Acquisition and Data-Rate Readback”, IEEE Journal of Solid-State Circuits, vol.40, no.12, pp. 2713-2725, Dec. 2005. [8] Y.Rong-Jyi, C, Kuan-Hua, H. Sy-Chyuan, L. Chuan-Kang, and L. Shen-Iuan, “A155.52 Mbps-3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit,” IEEE Journal of Solid-State Circuits, vol. 41, no.6, pp. 1380-1390, June 2006. [9] Seema Butala Anand and Behzad Razavi, “A CMOS Clock Recovery Circuit for 2.5-Gbs NRZ Data”, IEEE Journal of Solid-State Circuits, vol. 36, no.3, pp.432-439, Mar. 2001. [10] B.Razavi, “Challenges in the Design High-Speed Clock and Data Recovery Circuits”, IEEE Communication Magazine, vol.40, no.8, Mag., Aug. 2002. [11] C. Hogge, “A Self-Correcting Clock Recovery Circuit”, IEEE J. Light Wave Technology, vol. LT-3, pp. 1312-1314, Dec. 1985. [12] J. D. H. Alexander, “Clock Recovery from Random Binary Data”, Electronic Letters, vol. 11, no.22, pp. 41-542, Oct. 1975. [13] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”, IEEE Journal of Solid-State Circuits, vol. 36, no.5, pp761-767, May. 2001. [14] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With a Half-Hate Binary Phase/Frequency Detector”, IEEE Journal of Solid-State Circuits, vol. 38, no.1, pp13-21, January. 2003. [15] A. Pottbacker, U. Langman and H. Schreiber, “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8Gb/s”, IEEE Journal of Solid-State Circuits, vol. 27, no.12, pp. 1747-1751, Dec. 1992 [16] R. J. Yang, S. P. Chen and S. I. Liu, “A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet”, IEEE Journal of Solid-State Circuits, pp. 1356-1360, vol.39, no.8, Aug. 2004. [17] F. M. Gardner, “Properties of Frequency Difference Detectors”, IEEE Trans. Commun., vol.33, no2, pp. 131-138, Feb. 1985. [18] B. Razavi, “A 2.5-Gb/s 15-mW Clock Recovery Circuit”, IEEE Journal of Solid-State Circuits, vol. 31, no.4, pp. 472-480, Apr. 1996. [19] David G. Messerschmitt, “Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery”, IEEE Transactions on Communications, vol.27, no.9, pp. 1288-1295, Sep. 1979. [20] Shao-Hung Lin, Chang-Lin Hsieh, Shen-Iuan Liu, “A Half-Rate Bang-Bang Phase/Frequency Detector for Continuous-Rate CDR Circuits”, IEEE Conference on Electron Devices and Solid-State Circuits, pp. 353-356, 2007. [21] Jri Lee, Ke-Chung Wu, “A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit with Automatic Frequency Acquisition”, IEEE Journal of Solid-State Circuits, vol.44, no.12, pp.3590–3602, 2009. [22] Ohtomo, Y.; Nishimura, K.; Nogawa, M. “A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-um CMOS”, IEEE Journal of Solid-State Circuits, vol.41, no.9, pp. 2052–2057, Sep. 2006. [23] Chang-Lin Hsieh, Hong-Lin Chu, Shen-Iuan Liu, “A 10Gb/s Inductorless Quarter-Rate Clock and Data Recovery Circuit in 0.13um CMOS”, IEEE Asian Solid-State Circuits Conference, Page.165 – 168, 2009. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47108 | - |
dc.description.abstract | 在現代高速通訊中,序列通訊系統的傳輸速度已經達到每秒幾十憶位元.在現在的趨勢下,高速通訊系統的傳輸介質從銅線轉換到光纖.在局域網(LAN)和廣域網路(WAN)資料與時脈回復電路(CDR)的角色.它主要的功能是產生與輸入資料同步的時脈和把輸入資料的抖動量移除.另一方面,現今大部份的高速電路都都是利用互補式金屬氧化物半導體製程(CMOS)是因為它據有低成本,低消耗功率和高度的整合能力.
在設計資料與時脈回復電路時,通常會應用到電感來擴展電路的操作速度.不過,由於電感在晶片中佔據非常大的面積,若要用到電感,晶片的面積勢必大幅度增加.這不利於現在的趨勢, 晶片整合(SOC).另一方面,資料與時脈回復電路應該可以操作在不同速率增加可應用的範圍.所以在本篇論文提出一個無電感的半速率資料與時脈回復電路.它的操作範圍是6億位元每秒至7.7億位元每秒.電路包括一個能減少回復時脈抖動量和減輕壓控振盪器設計難度的線性半速率相位偵察器,一個俱有兩個獨立調控電壓的壓控振盪器,和一個已經包括頻率鎖定偵測器與不需參考時脈的頻率偵測器.本次晶片是由TSMC 90nm 1P9M CMOS 製程來實現,晶片面積是0.58毫米 x 0.58毫米.輸出時脈的峰對峰值抖動量為78ps,而其均方根值是12.64ps.當輸入資料是6Gb/s 27-1 PRBS時.在操作電壓是1.2伏特下,所消耗的功率為75.2毫瓦. | zh_TW |
dc.description.abstract | In high speed communication, the speed of serial communication has been increased to gigabits per second. The modern trend of high speed communication system converted the transmission medium from copper wire to fibre gradually. In the receiver side of networks, Clock and data recovery circuit (CDR) plays an important role for local area network (LANs) and wide area networks (WANS). The CDR circuit generates a clock that synchronizes with received data and removes the received data jitter. CMOS technologies are often employed in high-speed circuits now because of the low cost, low power dissipation and highly integrated capability.
CDR circuit usually uses inductors to expend the operation rate. However, the chip size must increase seriously because inductors occupy large area in die. It doesn’t benefit the modern trend, system on chip (SOC). On the other hand, the CDR should able to work in different speeds for different specifications. So an inductorless half-rate clock and data recovery circuit (6Gb/s-7.7Gb/s) was proposed. It is composed of a linear half-rate PD which can suppress jitter in retimed data and relax the design difficulty of VCO, a dual tuning VCO which have two independent tuning control voltage in order to reduce the clock jitter, finally, a reference-less FD which includes frequency locked detector that makes the FD is no output after frequency acquisition. The CDR was fabricated in TSMC 90nm 1P9M CMOS technology with an area of 0.58x0.58mm^2. The output clock jitter of this proposed CDR is measured 78ps (peak-to-peak) and 12.64ps (rms) for 6Gb/s 27-1 PRBS. The power dissipation of the core circuit is 75.2mW under 1.2V power supply. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T05:47:47Z (GMT). No. of bitstreams: 1 ntu-100-R97943125-1.pdf: 6143812 bytes, checksum: 2d281b6c33005287e48525a353d4d3f2 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | Table of Contents
Abstract iii Table of Contents v List of Figures vii List of Tables xi Chapter 1 Introduction 1 1-1 Motivation 1 1-2 Organization 2 Chapter 2 Basic Concepts of Fibre Optic Network 5 2-1 Introduction of Basic Concepts 5 2-1-1 Properties of Random Binary Data 5 2-1-2 Eye Diagram 7 2.2 Fibre Optic Transceiver 9 2-2-1 Optic Transmitter(TX) 9 2.2-2 Optic Receivers(RX) 10 2-2.3 Design Challenges of Optical Network 11 Chapter 3 Architecture of Clock and Data Recovery(CDR) 13 3-1 Introduction of Clock and Data Recovery 13 3-1-1 Referenced-less and Reference CDR 18 3-1-2 Half-Rate and Full-Rate CDR 19 3-1-3 Continue-rate CDR 21 3-1-4 Linear and Nonlinear CDR 23 3-2 Frequency Acquisition 25 3-3 Building Blocks of Clock and Data Recovery circuit 26 3-3-1 Phase Detector 26 3-3-2 Frequency Detector 35 3-3-3 Voltage Control Oscillator 40 3-4 Jitter Consideration in CDR Circuits 45 3-4-1 Jitter Transfer 45 3-4-2 Jitter Generation 46 3-4-3 Jitter Tolerance 46 3-5 Loop Filter parameter design 47 Chapter 4 Our Proposed CDR 51 4-1 Overall Architecture of Proposed CDR 51 4-2 Phase Detector 52 4-2-1 Latch, XOR and MUX 53 4-2-2 Charge Pump(CP) 55 4-3 Frequency Detector 56 4-3-1 Charge Pump(CP) 59 4-4 Voltage Control Oscillator(VCO) 61 4-5 Simulation result 64 4-5-1 Second Order Loop Filter 64 4-5-2 Behaviour Simulation 65 4-5-3 Transistor Level Simulation 67 4-5-4 Layout 71 Chapter 5 Experimental Result 73 5-1 Testing Environment Setup 73 5-2 Experimental Results 75 Chapter 6 Conclusion 81 Bibliography 83 | |
dc.language.iso | en | |
dc.title | 無電感半速率資料與時脈回復電路 | zh_TW |
dc.title | An Inductorless Half-Rate Clock and Data Recovery Circuit | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),李泰成(Tai-Cheng Lee) | |
dc.subject.keyword | 資料與時脈回復電路,壓控振盪器,線性半速率相位偵察器,頻率鎖定偵測器, | zh_TW |
dc.subject.keyword | Clock and Data Recovery Circuit,Voltage Control Oscillaotr,Linear half-rate phase detector,Frequency locking detector, | en |
dc.relation.page | 85 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-08-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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