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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭宇軒(Yu-Hsuan Kuo) | |
| dc.contributor.author | Chun-Chang Chen | en |
| dc.contributor.author | 陳羣昌 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:44:33Z | - |
| dc.date.available | 2010-08-20 | |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-19 | |
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Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, 'Three-dimensional silicon integration,' IBM J. of Research and Development, vol. 52, pp. 553-569, Nov. 2008. [20] T. Y. Kuo, S. M. Chang, Y. C. Shih, C. W. Chiang, C. K. Hsu, C. K. Lee, C. T. Lin, Y. H. Chen, and W. C. Lo, ' Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost,' 58th Electronic Components & Technology Conference, pp. 853-858, May 2008. [21] M. Umemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai, and K. Takahashi, 'High-performance vertical interconnection for high-density 3D chip stacking package,' Proc. 54th Electronic Components and Technology Conference, Vol. 1, pp. 616-623, Jun. 2004. [22] J. Q. Lu, Y. Kwon, G. Rajagopalan, M. Gupta, J. McMahon, K. W. Lee, R. P. Kraft, J. F. McDonald, T. S. Cale, R. J. Gutmann, B. Xu, E. Eisenbraun, J. Castracane, A. Kaloyeros, 'A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects,' Proc. of the IEEE Interconnect Technology Conference, pp. 78-80, Aug. 2002. [23] http://www.ansoft.com/products/hf/hfss/ [24] L. W. Schaper, S. L. Burkett, S. Spiesshoefer, G. V. Vangara, Z. Rahman, and S. Polamreddy, 'Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias,' IEEE Transactions on Advanced Packaging, vol. 28, pp. 356-366, Aug. 2005. [25] J. J. McMahon, E. Chan, S. H. Lee, R. J. Gutmann, and J. Q. Lu, 'Bonding interfaces in wafer-level metal adhesive bonded 3D integration,' 58th Electronic Components and Technology Conference, pp. 871 - 878, Jun. 2008. [26] A. Fan, A. Rahman, and R. Reif, 'Copper wafer bonding,' Electrochemical and Solid State Lett., vol. 2, pp. 534-536, Oct. 1999. [27] A. W. Topol, B. K. Furman, K. W. Guarini, L. Shi, G. M. Cohen, and G. F. Walker, 'Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures,' Proc. 54th Electronic Components and Technology Conference, Vol.1, pp. 931-938, Jun. 2004. [28] J. Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, M. Rasco, R. Augur, T. S. Cale, and R. J. Gutmann, 'Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs,' Proc. of the IEEE Interconnect Technology Conference, pp. 74-76, Jun. 2003. [29] J.D. Plummer, M. D. Deal, P. B. Griffin, 'Silicon VLSI technology: fundamentals, Practice and Modeling,' Prentice Hall, 2000. [30] S. Spiesshoefer, and L. Schaper, 'IC stacking technology using fine pitch nanoscale through silicon vias,' Proc. 53rd Electronic Components and Technology Conference, pp. 631-633, May 2003. [31] P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux, and R. Wieland, 'InterChip via technology for vertical system integration,' Proc. of the IEEE Interconnect Technology Conference, pp. 160-162, Jun. 2001. [32] M. T. Bohr, 'Interconnect scaling-the real limiter to high performance ULSI,' Proc. Electron Devices Meeting, pp. 241-244, Dec. 1995. [33] K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, and M. Koyanagi, 'Three-dimensional shared memory fabricated using wafer stacking technology,' International Electron Devices Meeting Technical Dig., pp. 165-168, Dec. 2000. [34] M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, 'Three-dimensional integration technology based on wafer bonding with vertical buried interconnections,' IEEE Transactions on Electron Devices, vol. 53, pp. 2799-2808, Nov. 2006. [35] K. Takahashi and M. Sekiguchi, 'Through silicon via and 3-D wafer chip stacking technology,' Symposium on VLSI Circuits Dig. of Technical Papers, pp. 114-117, Jun. 2006. [36] J. B. Lasky, 'Wafer bonding for silicon-on-insulator technologies,' Appl. Phys. Lett., vol. 48, pp. 78-80, Jan. 1986. [37] R. H. Havemann and J. A. Hutchby, 'High-performance interconnects: An integration overview,' Proc. of the IEEE, vol. 89, pp. 586-601, May 2001. [38] D. A. B. Miller, 'Rationale and challenges for optical interconnects to electronic chips,' Proc. of the IEEE, vol. 88, pp. 728-749, Jun. 2000. [39] D. A. B. Miller, 'Optical interconnects to silicon,' IEEE J. of Selected Topics in Quantum Electronics, vol. 6, pp. 1312-1317, Nov. 2000. [40] M. R. Feldman, S. C. Esener, C. C. Guest, and S. H. Lee, 'Comparison between optical and electrical interconnects based on power and speed considerations,' Appl. Optics, vol. 27, pp. 1742-1751, May 1988. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46980 | - |
| dc.description.abstract | 隨著積體電路的發展，元件越作越小。由電阻與電容所造成的延遲變的不可忽略，並且大大地影響到元件的操作速度。由於，一般傳統二維的積體式電路有著相當長的傳輸線，所以操作速度也因此大幅度的降低。為了減少元件與元件之間的傳輸線長度，三維的立體式電路應運而生。三維的立體式電路，不管是在功率的損枆、速度的延遲、頻寬和密度…等等都有很較好的表現。我們可以透過堆疊的方式來達成三維的立體式電路。一般而言，堆疊的方式大致上分為“wafer-to-wafer”和“die-to-wafer”兩種。連接各層電路的傳輸線，我們稱之為矽晶穿孔也就是所謂的垂直式傳輸線。在本篇論文裡，垂直式傳輸線有著相當重要的地位。
本研究主題主要分為兩個部份進行討論：(1)平面傳輸線；和(2) 垂直式傳輸線。首先，我們透過MATLABS去針對電阻與電容所造成的延遲進行模擬；並且利用HFSS模擬軟體去模擬傳輸線的頻寬。在量測時，為了減少傳輸損耗，我們採用了GSG (ground-signal-ground)探針，並且設計相對應的電極。透過半導體製程，長度長達三公分的傳輸線已經完成，它的頻寬大約為200MHz。我們為了要降低輸入損耗，針對不同的材料進行探討。將不同的金屬蒸鍍在鍺基板上，並且利用GSG探針進行量測。我們發現頻寬可達5GHz。其次，在垂直式傳輸線的部份，我們利用相當大量的SEM (scanning electron microscope)來進行孔洞的分析。孔洞的大小分別設計為10 × 10、20 × 20、50 × 50微米平方。我們透過乾蝕刻製程機台(ICP, inductive coupling plasma)去對孔洞進行深達100微米的蝕刻，並且利用蒸鍍的方式將鋁蒸鍍在孔洞的側壁與底部。 以三維的觀點而言，堆疊是一種相當有效且簡易的方式。我們可以透過平面傳輸線與垂直式傳輸線來實現三維立體式電路。並且可以將各式各樣的晶片整合在一起。 | zh_TW |
| dc.description.abstract | Following the CMOS transistor scaling down tendency, the effect of resistance and capacitance delay plays a decisive role. With the coplanar device, the interconnections between circuit and circuit are, relatively, very enormous, and then the resistance and capacitance delay cuts down the velocity of device very well. For reducing the average wire length of block-to-block interconnects, the three dimensional integration is an important key technique. Three-dimensional integration provides benefits for power efficiency, bandwidth, latency operation, performance and etc. For realizing the three-dimensional integration, the circuit is stacked one by one. Generally, stacking includes wafer-to-wafer, and die-to-wafer. The interconnections between stratum and stratum are using vias. In this thesis, via is a leading role.
The thesis is primarily divided into two parts：(1) interconnections, and (2) etching for vias. Firstly, we use MATLABS and HFSS to simulate RC delay and frequency response, respectively. For reducing the transmission loss, the pattern is designed for GSG measurement. Through the semiconductor fabrication, the length of 3cm interconnection is fabricated well. The bandwidth of 3cm interconnection is about 200 MHz. As a result of insertion loss, we take a discussion with different materials. The different materials are deposited on germanium substrate, and the bandwidth is up to 5 GHz. We find the silver has the more excellent transmittance. In the second part, via is etched by inductive coupling plasma (ICP). And the aluminum is deposited in the lateral and bottom of vias. Through image of scanning electron microscope, we can see the cross-section of via. A lot of cross-section SEM is using to analyze vias. The dimension of vias are 10 μm × 10 μm, 20 μm × 20 μm, and 50 μm × 50 μm. The deepest via is up to 100 μm. In the 3D viewpoint, stacking is a useful method. Though planar interconnection and via, we can realize the three-dimensional integration. The functions of a chip are more and more various, and the systems on chip (SOC) can be arrived. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:44:33Z (GMT). No. of bitstreams: 1 ntu-99-R97943088-1.pdf: 7260135 bytes, checksum: 206237b56371dc21ef483723973c6cac (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Contents
Abstract (Chinese).........................................I Abstract (English)........................................II Chapter 1：Introduction ...................................1 1.1 Interconnects & 3D integration ........................1 1.2 Thesis organization ...................................4 Chapter 2：Principles .....................................5 2.1 Principle of RC Delay .................................5 2.2 RC Simulation .........................................7 2.3 Interconnects Simulation ..............................9 2.4 Principle of GSG .....................................13 Chapter 3：Fabrication ...................................16 3.1 Fabrication ..........................................16 3.2 Interconnects ........................................16 3.3 Etching for Via ......................................23 Chapter 4：Measurement and Discussion ....................28 4.1 Interconnects Measurement Analysis ...................28 4.1.1 GSG Analysis .......................................28 4.1.2 Different materials Measurement Analysis ...........30 4.3 Etching for Via ......................................32 Chapter 5：Conclusion ....................................34 5.1 Conclusion ...........................................34 5.2 Future work ..........................................36 References ...............................................37 List of Figures Fig. 1-1. Diagram of 3D integration .......................3 Fig. 2-1. RC delay model ..................................6 Fig. 2-2. The schematic diagram of simulating structure ...8 Fig. 2-3. Diagram of τ vs. x & τ vs. L ...................8 Fig. 2-4. Tree diagram of the different analysis methods .10 Fig. 2-5. Block diagram of HFSS simulation setting up flow .....................................................10 Fig. 2-6. HFSS (a) the side-view of interconnections, and (b) the excitations of LumpPort1 .........................12 Fig. 2-7. Simulation of S parameters .....................12 Fig. 2-8. (a) GS probes ; (b) GSG probes .................15 Fig. 2-9. The dimension of GSG. (a) layout and (b) OM ....15 Fig. 3-1. The fabrication flow of self-alignment 3D ......17 Fig. 3-2. The fabrication flow of interconnects ..........17 Fig. 3-3. The image of over developed line pattern for line width of (a) 10 μm and (b) 50 μm ........................21 Fig. 3-4. The image of success developed line pattern for line width of (a) 10 μm, (b) 20 μm and (c) 50μm .........21 Fig. 3-5. Interconnects of evaporated Al for varying length/width：(a) 3-cm/20-μm, (b) 3-cm/50-μm, (c) 0.7-cm/10-μm, (d) 0.7-cm/20-μm, (e) 0.7-cm/50-μm ............22 Fig. 3-6. The fabrication flow of via ....................24 Fig. 3-7. Via array after exposed. Size of square：(a) 10 μm × 10 μm and (b) 20 μm × 20 μm .........................24 Fig. 3-8. After ICP etching. Size of square：(a) 10 × 10 μm2 and (b) 20 × 20 μm2 ..................................27 Fig. 3-9. After oxide deposition. Size of square：(a) 10 × 10 μm2 and (b) 20 × 20 μm2 ..............................27 Fig. 3-10. After Al deposition. Size of square：(a) 10 × 10 μm2 and (b) 20 × 20 μm2 .................................27 Fig.4-1. The high speed measurement system with GSG probe ....................................................29 Fig. 4-2. The frequency response of 3 cm interconnects ...29 Fig. 4-3. Frequency response of different materials ......31 Fig. 4-4. SEM. (a) deep via, and (b) 10 μm via with oxide and Al deposited .........................................33 Fig. 4-5. SEM. (a) lateral via, and (b) bottom of via ....33 | |
| dc.language.iso | en | |
| dc.subject | 孔洞 | zh_TW |
| dc.subject | 傳輸線 | zh_TW |
| dc.subject | 立體式 | zh_TW |
| dc.subject | via | en |
| dc.subject | three-dimension | en |
| dc.subject | interconnects | en |
| dc.title | 傳輸線與立體式電路集成 | zh_TW |
| dc.title | Interconnects & 3D Integration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋(Yi-Chang Lu),蔡坤諭(Kun-Yu Tsai) | |
| dc.subject.keyword | 傳輸線,立體式,孔洞, | zh_TW |
| dc.subject.keyword | interconnects,three-dimension,via, | en |
| dc.relation.page | 43 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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