請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46893完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士(Shey-Shi Lu) | |
| dc.contributor.author | Yu-Lun Chang | en |
| dc.contributor.author | 張育綸 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:42:52Z | - |
| dc.date.available | 2013-08-20 | |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-20 | |
| dc.identifier.citation | [1] Chii-Wann Lin, Hung-Wei Chiu, Mu-Lien Lin, Chi-Heng Chang, I-Hsiu Ho, Po Hsiang Fang, Yi Chin Li, Chang Lun Wang, Yao-Chuan Tsai, Yeong-Ray Wen, Win-Pin Shih, Yao-Joe Yang, Shey-Shi Lu, “Pain Control On Demand Based on Pulsed Radio- Frequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC”, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
[2] 莊勝富, “Layout of a Resistor-String Successive Reference Generator”, July 2007. [3] Che-Wei Chang, “Design and Application of Analog-to-Digital Converter”, July 2007. [4] Seung-Tak Ryu, Bang-Sup Song, and Kantilal Bacrania, “A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007 [5] Chris Toumazou, George S. Moschytz, Barrie Gilbert, “Trade-Offs in Analog Circuit Design – The Designer’s Companion”, 2002. [6] Chunlei Shi, Mohammed Ismail, “Data Converters for Wireless Standards”, 2001. [7] Franco Maloberti, “Data Converters”, 2007. [8] David A. Johns, Ken Martin, “Analog Integrated Circuit Design”, 1997. [9] B. Razavi, “Design of Analog CMOS Integrated Circuits”, 2001. [10] Po-Hsiang Fang, “Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters”, June 2009. [11] Lapoe Lynn, Paul Ferguson Jr., “A Capacitor-Based D/A Converter with Continuous Time Output for Low-Power Applications”. [12] Vipul Katyal, Randall L. Geiger, and Degang J. Chen, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, APCCAS, 2006. [13] Timothy M. Hancock, Scott M. Pernia, and Adam C. Zeeb, “A Digitally Corrected 1.5-Bit/Stage Low-Power 80 Ms/s 10-Bit Pipelined ADC”, EECS 598-02, December 2002. [14] J. W. Yang and K. W. Martin, “High-Resolution Low-Power CMOS D/A Converter”, IEEE J. of Solid-State Circuits, Vol. 24, pp. 1458-1461, October 1989. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46893 | - |
| dc.description.abstract | 在本論文的第三章，我們將介紹一個解析度為六位元，轉換頻率為一百萬赫茲的電容切換式數位類比轉換器。此轉換器將整合在神經刺激器裡，作為一任意波型產生器，以提供不僅止於方波的刺激波形。
在第四章，我們將介紹一個解析度十位元，轉換頻率為一百萬赫茲的數位類比轉換器。此轉換器使用我們所新提出的電容電阻混合式架構，相較於其他傳統架構可在較少面積和功率消耗之下達到高解析度。 第五章將介紹一個解析度十位元，轉換頻率為五十百萬赫茲的管線式類比數位轉換器。利用電流重複運用的技巧，和傳統管線式架構相比可減少約一半的類比功率消耗。 本論文裡的所有晶片皆使用TSMC 2P4M 0.35μm CMOS的製程來設計和實現。 | zh_TW |
| dc.description.abstract | In Chapter 3, a 6-bit, 1MHz, low power DAC is presented. This chip is designed to be an arbitrary waveform generator for the neural stimulator.
In Chapter 4, a 10-bit, 1MHz, low power DAC using the proposed “C-R hybrid architecture” is presented. With this architecture, the DAC can achieve high resolution while using lower power and smaller area comparing with other architecture. In Chapter 5, a 10-bit, 50MHz, pipelined ADC is presented. By using the “opamp current reuse technique”, the analog power consumption is reduced by half comparing with the conventional pipelined ADC. All chips in this thesis are designed and fabricated using TSMC 2P4M 0.35μm CMOS technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:42:52Z (GMT). No. of bitstreams: 1 ntu-99-R97943056-1.pdf: 31698340 bytes, checksum: 99b88a27e798e6ca161f01b78a854502 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 Fundamentals of Data Converters 4 2.1 Types of Converters 5 2.2 Data Converters Specifications 6 2.2.1 General Features 6 2.2.2 Static Specifications 8 2.2.3 Dynamic Specifications 10 2.3 Digital-to-Analog Converter Architectures 14 2.3.1 Current Steering DAC 14 2.3.2 Resistor Based DAC 16 2.3.3 Capacitor Based DAC 18 2.4 Analog-to-Digital Converter Architectures 19 2.4.1 Flash ADC 19 2.4.2 Successive Approximation ADC (SAR ADC) 20 2.4.3 Pipelined ADC 21 Chapter 3 A 6-bit, 1MHz, Low Power Switched- Capacitor DAC for Stimulator 23 3.1 Motivation and Introduction 23 3.2 Architecture of Switched-capacitor DAC with Continuous-time Output 24 3.3 6-bit DAC Circuit Design 26 3.3.1 Operational Amplifier 26 3.3.2 Capacitor Array 30 3.3.3 Clock Generator 32 3.4 6-bit DAC Whole Chip Simulations 33 3.4.1 Static Performance Simulations 33 3.4.2 Dynamic Performance Simulations 34 3.5 6-bit DAC Measurement 35 3.5.1 Printed Circuit Board Design 36 3.5.2 Measurement Setup 37 3.5.3 Static Performance Measurement 38 3.5.4 Dynamic Performance Measurement 40 3.6 6-Bit DAC Performance Summary 42 Chapter 4 A 10-bit, 1MHz, Low Power C-R Hybrid DAC 43 4.1 Motivation and Introduction 43 4.2 Proposed Architecture of Capacitor-Resistor Hybrid DAC 45 4.3 10-bit Hybrid DAC Circuit Design 47 4.3.1 Clock Generator 48 4.3.2 Operational Amplifier 48 4.3.3 Capacitor Array 48 4.3.4 Resistor String 49 4.4 10-bit Hybrid DAC Simulations 50 4.4.1 Static Performance Simulations 51 4.4.2 Dynamic Performance Simulations 52 4.5 10-bit Hybrid DAC Measurement 53 4.5.1 Printed Circuit Board Design 54 4.5.2 Measurement Setup 54 4.5.3 Static Performance Measurement 55 4.5.4 Dynamic Performance Measurement 55 4.6 10-Bit Hybrid DAC Performance Summary 58 Chapter 5 A 10-bit, 50MHz, Pipelined ADC with Opamp Current Re-use 59 5.1 Motivation and Introduction 59 5.2 Architecture of Pipelined ADC 60 5.2.1 Pipelined ADC System Architecture 60 5.2.2 1.5-bit per Stage & Digital Error Correction Technique 61 5.2.3 Previous Opamp Power Saving Techniques 63 5.2.4 Opamp Current Reuse Technique 65 5.3 Pipelined ADC Circuit Design 66 5.3.1 Operational Amplifier 66 5.3.2 Front-end Sample-and-hold Stage 70 5.3.3 Multiplying DAC (MDAC) 72 5.3.4 Dynamic Comparator 73 5.3.5 Clock Generator 74 5.3.6 Digital Error Correction Circuit 75 5.4 Pipelined ADC Simulations 76 5.4.1 Static Performance Simulations 77 5.4.2 Dynamic Performance Simulations 77 5.5 Pipelined ADC Measurement 79 5.5.1 Printed Circuit Board Design 80 5.5.2 Measurement Setup 81 5.5.3 Measurement 82 5.6 Pipelined ADC Performance Summary 85 Chapter 6 The 18-Copper-Man Demo Project 86 6.1 Motivation and Introduction 86 6.2 System Implementation 87 6.3 Transmitter Module 89 6.4 Digital Module 91 6.5 Measurement 93 Chapter 7 Conclusion 97 References 99 | |
| dc.language.iso | en | |
| dc.title | 類比數位轉換器及數位類比轉換器之設計與應用 | zh_TW |
| dc.title | Design and Application of Analog-to-Digital Converters and Digital-to-Analog Converters | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,孟慶宗,邱弘緯,陳筱青 | |
| dc.subject.keyword | 數位類比轉換器,類比數位轉換器,電容切換式,混合式,管線式, | zh_TW |
| dc.subject.keyword | DAC,ADC,Switched-Capacitor,Hybrid,Pipelined, | en |
| dc.relation.page | 100 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-99-1.pdf 目前未授權公開取用 | 30.96 MB | Adobe PDF |
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