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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇(An-Yeu Wu) | |
| dc.contributor.author | Hao-Yu Wang | en |
| dc.contributor.author | 王浩宇 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:26:30Z | - |
| dc.date.available | 2010-07-20 | |
| dc.date.copyright | 2010-07-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-15 | |
| dc.identifier.citation | [1] ITRS, International Technology Roadmap for Semiconductors, [Online]. Available: http://public.itrs.net.
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Mishra, Y. Xie, N. Vijaykrishnan, and C. Das, “MIRA: A multi-layered on-chip interconnect router architecture,” in Proc. IEEE Int. Symp. Computer Architecture (ISCA), pp. 251-261, 2008. [18] C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, “Three-dimensional chip-multiprocessor run-time thermal management,” IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, Aug. 2008. [19] L. Shang, L. Peh, A. Kumar, and N.K. Jha, “Thermal modeling, characterization and management of on-chip networks,” in Proc. IEEE/ACM Int. Symp. Microarchitecture, pp. 67-78, 2004. [20] J. Torresola, Chia-Pin Chiu, G. Chrysler, D. Grannes, R. Mahajan, R. Prasher and A. Watwe, “Density factor approach to representing impact of die power maps on thermal management.” IEEE Trans. Advanced Packaging. vol. 28, no. 4, pp. 659-664. Nov. 2005. [21] C. Addo-Quaye, 'Thermal-aware mapping and placement for 3-D NoC designs,' in Proc. IEEE Int. SOC Conference, pp.25-28, Sept. 2005. [22] C. H. Chao, K. Y. Jheng, H. Y. Wang, J. C. Wu, and A. Y. Wu, “Traffic and thermal-aware run-time thermal management scheme for 3D NoC systems,” in Proc. IEEE/ACM Int. Symp. Networks-on-Chip, pp.223-230, May 2010. [23] J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan , M. Yousif, and C. Das, “A novel dimensionally-decomposed router for on-chip communication in 3D architectures,” in Proc. IEEE Int. Symp. Computer Architecture (ISCA), pp. 138-149, 2007. [24] G. M. Chiu, 'The odd-even turn model for adaptive routing,' IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July, 2000. [25] G. Ascia, V. Catania, M. Palesi and D. Patti, “Neighbors-on-Path: A new selection strategy for on-chip networks,” in Proc. IEEE/ACM/IFIP Workshop on Embedded Systems For Real Time Multimedia, Oct. 2006. [26] P. Gratz, B. Grot, and S. W. Keckler, 'Regional congestion awareness for load balance in networks-on-chip,' in Proc. IEEE Symp. High Performance Computer Architecture (HPCA), pp.203-214, Feb. 2008. [27] J. Hu and R. Marculescu, “Application-specific buffer space allocation for networks-on-chip router design,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 2004. [28] Noxim: Network-on-Chip Simulator [On-line]. Available: http://sourceforge.net/projects/noxim [29] W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron, “An improved HotSpot block-based thermal model with granularity considerations,” in Workshop on Duplicating, Deconstructing, and Debunking (WDDD), in conjunction with Intl. Symp. on Computer Architecture (ISCA), June 2007. [30] Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, 'A 5-GHz mesh interconnect for a teraflops processor,' Micro, IEEE , vol. 27, no. 5, pp. 51-61, Sep.-Oct. 2007. [31] C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” J. ACM, vol. 41, no. 5, pp. 874-902, Sep. 1994. [32] K. Y. Jheng, C. H. Chao, H. Y. Wang and A. Y. Wu, “Traffic-thermal mutual-coupling co-simulation platform for three-dimensional Network-on-Chip,” in Proc. IEEE Int. Symp. VLSI Design, Automation & Test (VLSI-DAT), pp.135-138, Apr. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46737 | - |
| dc.description.abstract | 本篇論文針對三維晶片網路之熱感知設計的效能降低做出改善。我們分別提出兩種設計技巧：1) 針對過熱關閉元件之三維晶片網路下的可適性路由演算法 2) 針對流量遷移的資源分配演算法。為了促進三維晶片網路之熱感知設計與相關研究，我們亦提出模擬平台：3) 針對三維晶片網路的流量-溫度共同模擬平台。對於過熱關閉造成的流量阻塞，我們提出一可適性路由演算法以改善網路效能。此可適性路由演算法基於奇偶路由法，能感知網路上的流量資訊以及過熱關閉資訊，進而自動選擇適當路徑，使封包能繞開過熱關閉元件以及平衡網路負載。由於能降低三維晶片網路的穩態溫度的流量遷移，帶來各層不平衡的網路負載並造成流量阻塞。我們針對流量遷移提出一資源分配演算法，藉由分配不同層上路由器上的緩衝器深度，平衡各層的網路負載，進而改善網路效能。因為現行模擬平台缺乏支援流量與溫度的共同模擬，我們自行開發一模擬平台，以支援上述兩種熱感知設計與相關效能改進技術。此模擬平台亦經由商用溫度模型工具驗證其垂直面的熱傳導模擬，以確保相對性上的正確度。 | zh_TW |
| dc.description.abstract | In this thesis, we proposed two techniques to improve the performance degradation of thermal-aware 3D NoC designs: 1) Adaptive routing for throttled 3D NoC. 2) Resource allocation for traffic migration. And we also proposed: 3) a traffic-thermal co-simulation platform for 3D NoC to facilitate the two kinds of thermal-aware design. To address the traffic congestion due to throttling of transient-temperature control, we proposed an adaptive routing algorithm. Based on the Odd-Even routing function, a traffic- and throttling-aware selection strategy is proposed to decide proper routing path to balance network traffic and detour throttled tiles. While the traffic congestion happens after the traffic migration of steady-temperature optimization, we proposed a design flow of resource allocation. Depend on the loading requirement at each layer, our allocation assigns suitable buffer depth for each layer under a constraint of total buffer cost. Our proposed simulation platform supports unidirectional coupling and mutual coupling. And we validate the proposed simulation platform with commercial thermal modeling tool, CFD-RC, to assure the relative correctness of vertical heat conduction. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:26:30Z (GMT). No. of bitstreams: 1 ntu-99-R97943123-1.pdf: 2011089 bytes, checksum: f0bad639503c2023c17a46beea9d2d67 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 中文摘要 i
ABSTRACT ii CONTENTS iii LIST OF FIGURES vi LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Motivation and Goal 1 1.1.1 On-Chip Communication Trend 1 1.1.2 3D IC and 3D Network-on-Chip 2 1.1.3 Thermal Issue of 3D Network-on-Chip 5 1.1.4 Thermal-Aware Designs for 3D Network-on-Chip 7 1.1.5 Performance Issue of Thermal-Aware Design 9 1.1.6 Simulation Platform for 3D NoC Design 12 1.1.7 Goal 13 1.2 Thesis Organization 14 Chapter 2 Related Works 15 2.1 Router Architecture for 3D NoC 15 2.1.1 Dimensionally-Decomposed Router for 3D NoC 15 2.2 Thermal Management for Network-on-Chip 17 2.2.1 ThermalHerd 17 2.2.2 Thermal Management for 3D NoC 19 2.2.3 Summary of Thermal Management 21 2.3 Adaptive Routing without Virtual Channel 22 2.3.1 Odd-Even Adaptive Routing 22 2.3.2 Neighbor-on-Path Selection Strategy 22 2.3.3 Selection Strategy of Regional Congestion Awareness 23 2.3.4 Summary of Selection Strategy 24 2.4 Resource Allocation 25 2.4.1 Application-Specific Buffer Space Allocation 25 Chapter 3 Adaptive Routing Algorithm for Throttled 3D NoC 27 3.1 Traffic Balancing in Throttled 3D NoC 27 3.2 Routing Function for 3D NoC 29 3.3 Selection Function for 3D NoC 30 3.3.1 Utilization of DimDe Router Architecture 31 3.3.2 Traffic- and Throttling-Aware Selection Strategy 32 Chapter 4 Resource Allocation for Traffic Migration 35 4.1 Asymmetric 3D NoC for Traffic Migration 35 4.1.1 Congestion of Traffic Migration in Symmetric 3D NoC 35 4.1.2 Design Space of Buffer Allocation for 3D NoC 37 4.2 Mathematical Model for Rapid Network Simulation 38 4.2.1 The Finite Queue M/M/1/k Model 38 4.2.2 Queuing Model for 3D NoC Routers 40 4.3 Design Flow of Buffer Allocation 42 Chapter 5 Performance Evaluation 44 5.1 Traffic-Thermal Co-Simulation Platform for 3D NoC 44 5.1.1 Framework of Co-Simulation Platform 44 5.1.2 Validation with CFD-RC 45 5.2 Resource Allocation for 3D NoC 46 5.2.1 Uniform Traffic Pattern 46 5.2.2 Transpose Traffic Pattern 48 5.3 Adaptive Routing for Throttling NoC 49 5.3.1 Uniform Traffic Pattern 50 5.3.2 Transpose Traffic Pattern 51 Chapter 6 Conclusion and Future Works 53 6.1 Conclusion 53 6.2 Future Works 54 REFERENCE 55 Curriculum Vitae 59 | |
| dc.language.iso | en | |
| dc.subject | 路由演算法 | zh_TW |
| dc.subject | 三維晶片 | zh_TW |
| dc.subject | 晶片內網路 | zh_TW |
| dc.subject | 熱感知 | zh_TW |
| dc.subject | 資源分配 | zh_TW |
| dc.subject | Network-on-Chip | en |
| dc.subject | routing algorithm | en |
| dc.subject | resource allocation | en |
| dc.subject | thermal-aware | en |
| dc.subject | 3D IC | en |
| dc.title | 適用於熱感知三維晶片網路之資源分配與可適性路由演算法 | zh_TW |
| dc.title | Resource Allocation and Adaptive Routing Algorithm for Thermal-Aware Three-Dimensional Network-on-Chip | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曾紹崟(Shau-Yin Tseng),許明華(Ming-Hwa Sheu),盧奕璋(Yi-Chang Lu) | |
| dc.subject.keyword | 三維晶片,晶片內網路,熱感知,資源分配,路由演算法, | zh_TW |
| dc.subject.keyword | 3D IC,Network-on-Chip,thermal-aware,resource allocation,routing algorithm, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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