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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
dc.contributor.author | Chih-Jung Hsu | en |
dc.contributor.author | 徐志榮 | zh_TW |
dc.date.accessioned | 2021-06-15T05:09:40Z | - |
dc.date.available | 2012-07-26 | |
dc.date.copyright | 2010-07-26 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-07-26 | |
dc.identifier.citation | 1.Double Data Rate (DDR) SDRAM Standard, JEDEC Standard. (2008, Feb.). [Online], Available: http://www.jedec.org.
2.Double Data Rate 2 (DDR2) SDRAM Standard, JEDEC Standard. (2009, Nov.). [Online]. Available: http://www.jedec.org. 3.Double Data Rate 3 (DDR3) SDRAM Standard, JEDEC Standard. (2009, Sep.). [Online]. Available: http://www.jedec.org. 4.International Technology Roadmap for Semiconductors. London, U.K. (2008). [Online]. Available: http://www.itrs.net/ 5.S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs. Hoboken NJ: Wiley 2009. 6.T.-L. Wu, H.-H. Chuang, and T.-K. Wang, “Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation,” IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp. 346–356, May 2010. 7.G. Kim, D. G. Kam, and J. Kim, “TDR/TDT analysis by crosstalk in single and differential meander delays for high speed PCB application,” in Proc. IEEE Conf. Rec., 2006, vol. 3, pp. 657–662. 8.K.-T. Hsu, G.-H. Shiue, C.-M. Lin, T.-W. Huang, and R.-B. Wu, “Design of reflectionless vias using neural network-based approach,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 1, pp. 211–218, Feb. 2008. 9.G.-H. Shiue, W.-D. Guo, C.-M. Lin, and R.-B. Wu, “Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines,” IEEE Trans. Adv. Packag., vol. 29, pp. 560-569, Aug. 2006. 10.L. Smith, “Simultaneous switch noise and power plane bounce for CMOS technology,” in Proc. IEEE Top. Meeting Electr. Perform. Electron. Packag., Oct. 1999, pp. 163–165. 11.J.-N. Hwang and T.-L. Wu, “Coupling of the ground bounce noise to the signal trace with via transition in partitioned power bus of PCB,” in Proc. IEEE EMC Symp., Aug. 2002, vol. 2, pp. 733–736. 12.J. Kim, M. Rotaru, S. Baek, J. Park, M. Iyer, and J. Kim, “Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards,” IEEE Trans. Electromagn. Compat., vol. 48, no. 2, pp. 319–330, May 2006. 13.M. Swaminathan and A. Ege Engin, Power Integrity Modeling and Design for Semiconductors and Systems. Englewood Cliffs, NJ: Prentice-Hall, 2007. 14.C. Wyland , and W. Nunn, “Signal integrity study of 1000 ball grid array package construction effects on DDR2 at 533MHZ,” in Proc. IEEE Electr. Perform. Electron. Packag., oct 2003. 15.J.-H. Kim, W. Kim, D. Oh, R. Schmitt, J. Feng, C. Yuan, L. Luo, and J. Wilson, “Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems, ” in Proc. IEEE Electr. Perform. Electron. Packag., oct 2007. 16.J. Ren, D. Oh, S. Chang, and F. Lambrecht, “Statistical Link Analysis of High-Speed Memory I/O Interfaces during Simultaneous Switching Events,” in Proc. IEEE Electr. Perform. Electron. Packag., oct 2008. 17.J-H. Kim, R. Schmitt, D. Oh, W. T. Beyene, M. Li, A. Vaidyanath, Y. Lu, J. Feng, C. Yuan, D. Secker, and D. Mullen, “Design of Low Cost QFP Packages for Multi-Gigabit Memory Interface, ” , in Proc. IEEE Electron. Compo. and Technol. Conf., May 2009. 18.H.-H. Chuang, W.-D. Guo, Y.-H. Lin, H.-S. Chen, Y-C Lu, J. Hong, C.-H. Yu, A. Cheng, J. Chou, C.-J. Chang, J. Ku, T.-L. Wu, and R.-B. Wu, “Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Co-Analysis,” IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp. 381–391, May 2010. 19.J. Hsu and R. Hsiao, “High-speed GDDRIII System Implementation by Channel Signal and Power Integrity Factorial Design, ” in Proc. IEEE Electron. Compo. and Technol. Conf., May 2007. 20.W.-Y. Yip, S. Best, W. Beyene, and R. Schmitt, “System Co-Design and Co-Analysis Approach to Implementing the XDR™ Memory System of the Cell Broadband Engine™ Processor,” in Proc. Asia South Pacific Design Automation Conf., Jan. 2007. 21.D.-B. Lin, M.-P. Houng, and W.-S. Liu, ” Enhancement of Signal Integrity for Multi-Module Memory Bus by Particle Swarm Optimization,” in Proc. IEEE. Wireless and Microw Technol. Conf., Apr 2010. 22.H. B. Dwight, “Skin Effect and Proximity Effect in Tubular Conductors,” Trans. Am. Inst. Electr. Vol. XLI, pp. 189 - pp. 198, Jan. 1922 23.H. B. Dwight, “Proximity Effect in Wires and Thin Tubes,” Trans. Am. Inst. Electr., Vol. XLII, pp. 850 - pp. 859, Jan. 1923 24.T. Granberg, Handbook of Digital Techniques for High-Speed Design: Design Examples, Signaling and Memory Techniques, Fiber Optics, Modeling and Simulation to Ensure Signal Integrity. Upper Saddle River, NJ: Prentice-Hall, 2004. 25.E. Engin, M. Coenen, H. Koehne, G. Sommer, W. John, “Three-Pole Analysis Model to Predict SI and EMC Effects”, in Proc. EMC Compo, Toulouse, France, Nov.2002. 26.K. Radhakrishnan , Y. Li, and W. P. Pinello, “Integrated Modeling Methodology for Core and I/O Power Delivery”, in Proc. IEEE Electron. Compo. and Technol. Conf., Orlando, May. 2001, pp. 1107-1110. 27.R. Schmitt, J. -H. Kim, D. Oh, C. Yuan, 'Power delivery design for 800 MHz DDR2 memory systems in low-cost wire-bond packages,' in Proc. IEEE Electron. Packag. Technol. Conf., pp. 222-228, Dec. 2006 28.H-spice, ver. 2008.03, Synopsis, Natick, MA 29.Y. H Lin, J. Chou, Y. C Lu, T. L Wu, and H. S Chen, “Chip-Package-Board Co-design - a DDR3 System Design Example from Circuit Designers’ in Proc. Electr. Design Adv. Packag. Syst., Seoul, Korea, Dec.2008, pp. 27–30. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46450 | - |
dc.description.abstract | 本文針對高速記憶體中符合載線串聯終止邏輯電路(stub series terminated logic, SSTL)架構下的輸入/輸出電路(input/output circuits, I/O circuits),在同時考慮系統信號完整性(signal integrity, SI)與電源完整性(power integrity, PI)的表現下,提出一種結合晶片—封裝結構的共模擬分析與設計方式。基於電路在暫態切換時的電流特性,本文提出三個用於評估高速記憶體電路封裝結構在信號完整性及電源完整性表現的設計參數。簡化的晶片與封裝結構分別被設計實做並進行量測,並與共模擬資料比較以驗證上述之想法。為了使動態記憶體(dynamic random access memory ,DRAM)設計者能讓電路達到更好的表現,在此將分析與設計的方法有系統的整理為一套設計流程。理論實用的部分則依照此設計流程來改善商業用DDR3記憶體模組之封裝結構。在相同佈局面積的限制條件下,原本總體表現最糟的電路組在輸入信號資料傳輸速率為5Gb/s下於輸出信號的眼高及電源端之電壓擾動分別有16.1%與10.1%的改善。 | zh_TW |
dc.description.abstract | To obtain better performance in signal integrity (SI) and power integrity (PI) of high-speed memory circuits, the co-analysis and design of chip-package structures under stub series terminated logic (SSTL) topology are demonstrated. Based on the characteristic current flow, three package design parameters: Ldiff, LPDN, and Lloop, are proposed to evaluate the PI and SI performance of high-speed memory input/output (I/O) circuits. The chip-package co-simulation and measurement at time-domain have reached a good agreement in both PI part and SI part to verify the ideas. A systematic design flow is constructed for dynamic random access memory (DRAM) designers to obtain better SI and PI performance. Under the design flow, an application study to improve a commercial DDR3 package, which refines from a real package substrate, is presented to have better performance in SI and PI under the condition of identical layout area. The eye-height of output signal and voltage variation of the worst case have been improved 16.1% and 10.1% at data-rate 5 Gb/s, respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T05:09:40Z (GMT). No. of bitstreams: 1 ntu-99-R97942002-1.pdf: 63487681 bytes, checksum: f1956c5a2e161b72c950e6e37cca3c41 (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | Table of Contents
誌謝…I 中文摘要…Ⅱ Abstract…Ⅲ Table of ContentsIV List of Figures…VI List of Tables…X Acronyms…XI Chapter 1 Introduction…1 1.1 Research Motivations…1 1.2 SI/PI Issues for High-Speed Memory I/O Circuits…2 1.3 Proposed Research and Dissertation Outline …6 Chapter 2 Analysis for High-Speed I/O Circuits…8 2.1 Physical Structure of High-Speed I/O Circuits…8 2.2 SSTL Termination Structure11…11 2.3 Modeling of High-Speed Memory OCD…12 Chapter 3 Package Design Strategy for SI/PI issues…19 3.1 Transient Current Flow Analyses under SSTL Structure…19 3.2 PI Issues Analysis and Package Design Strategy…23 3.2.1 Network Analysis in Frequency-Domain…24 3.2.2 Iloop and Icrowbar in Frequency-Domain…30 3.2.3 Package Design Strategy for PI Part…37 3.2.4 Conclusions for PI Part…43 3.3 SI Issues Analysis and Package Design Strategy…44 3.3.1 Derivation of Time-domain Current and Output Signal…44 3.3.2 Package Design Strategy for SI Part…53 3.3.3 Conclusions for SI Part…58 Chapter 4 Application Case Studies…59 4.1 Chip-Package Co-Simulation and Measurement…59 4.1.1 The simplified OCD design…59 4.1.2 The package design for OCD measurement…64 4.1.3 PI design strategy validation…72 4.1.4 SI design strategy validation…75 4.1.5 Conclusion…79 4.2 Commercial DRAM Package Layout Modification…80 Chapter 5 Conclusions…87 References…89 | |
dc.language.iso | en | |
dc.title | 針對高速記憶體輸入/輸出介面之信號/電源完整性晶片—封裝共模擬分析與設計 | zh_TW |
dc.title | Chip-Package Co-Analysis and Design for SI/PI Issues of High-Speed Memory I/O Interfaces | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳瑞北(Ruey-Beei Wu),陳信樹(Hsin-Shu Chen),陳仁君(Jen-Jun Chen) | |
dc.subject.keyword | 載線串聯終止邏輯電路,輸入/輸出電路,信號完整性,電源完整性,動態記憶體, | zh_TW |
dc.subject.keyword | stub series terminated logic (SSTL),signal integrity (SI),power integrity (PI),input/output (I/O) circuits,dynamic random access memory (DRAM), | en |
dc.relation.page | 93 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2010-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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