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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46272完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Feipei, Lai) | |
| dc.contributor.author | I-Jui Tung | en |
| dc.contributor.author | 童顗叡 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:01:03Z | - |
| dc.date.available | 2010-07-30 | |
| dc.date.copyright | 2010-07-30 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-27 | |
| dc.identifier.citation | [1] E. P, et al., 'Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines,' ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation, 2009.
[2] Approved IEEE Draft Standard SystemC Language Reference Manual (superseded by 1666-2005). In IEEE Std. P1666/D2.1.1, 2005. [3] L. T. Clark, C. Byungwoo, and M. Wilkerson, 'Reducing translation lookaside buffer active power,' in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 10-13. [4] V. Chaudhary, T. H. Chen, F. Sheerin, and L. T. Clark, 'Critical race-free low-power nand match line content addressable memory tagged cache memory,' IET Computers & Digital Techniques, vol. 2, no. 1, pp. 40-44, Jan. 2008. [5] C.-C. Wu, S.-H. Wen, N.-F. Huang, and C.-N. Kao, 'A pattern matching coprocessor for deep and large signature set in network security system,' in IEEE Global Telecommunications Conference (GLOBECOM), 2005, p. 5. [6] K. Pagiamtzis and A. Sheikholeslami, 'Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,' IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006. [7] K. J. Schultz, 'Content-addressable memory core cells: a survey,' Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997. [8] C.-S. Lin, J.-C. Chang, and B.-D. Liu, 'A low-power precomputation-based fully parallel content-addressable memory,' IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 654-662, Apr. 2003. [9] S.-J. Ruan, C.-Y. Wu, and J.-Y. Hsieh, 'Low Power Design of Precomputation-Based Content-Addressable Memory,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3, pp. 331-335, Mar. 2008. [10] C.-Y. Wu, S.-J. Ruan, C.-K. Cheng, and M.-B. Lin, 'A new Block-XOR precomputation-based CAM design for low-power embedded system,' in IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, pp. 1-4. [11] J.-Y. Hsieh and S.-J. Ruan, 'Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm,' in Asia and South Pacific Design Automation Conference (ASPDAC), 2008, pp. 316-321. [12] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, 'MiBench: A free, commercially representative embedded benchmark suite,' in IEEE International Workshop on Workload Characterization (WWC-4), 2001, pp. 3-14. [13] Noxim. Available: http://noxim.sourceforge.net/ [14] Ilion Yi-Liang Hsiao; Ding-Hao Wang; Chein-Wei Jen; , 'Power modeling and low-power design of content addressable memories ,' Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol.4, no., pp.926-929 vol. 4, 6-9 May 2001 [15] P. Herber, et al., 'Model checking SystemC designs using timed automata,' presented at the Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pp. 131-136, 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46272 | - |
| dc.description.abstract | 因為內容可定址記憶體具有高速搜尋的特性，使得它廣泛地用來實現網路路由器的IP查看表。IPv6中，網路位址增加到128個位元數，因此可以預期內容可定址記憶體的儲存容量將會越來越大。模擬時間是影響上市日期的重要因素。在內容可定址記憶體的早期設計階段使用電晶體層的模擬，例如SPICE，將耗費大量時間並且延遲了產品上市日期。SystemC為系統層級的模擬語言與平台，它提供了較佳的模擬效率以及軟硬體共同設計的能力。然而SystemC並未提供量測耗電量的函式。我們開發早期設計階段SystemC的內容可定址記憶體match-line耗電量測量工具，並建立新的內容可定址記憶體match-line的耗電公式，並模擬了Mibench中十個測量基準，進而將SPICE和SystemC的模擬結果做比較。利用我們的工具，模擬時間平均加快1654倍，而match-line, search-line, storage cell耗電量預估的誤差比平均為14.79%, 11.681%, 3.66%。除此之外我們更提出針對gate-block selection algorithm的低功率改進方案，資料比較次數，錯誤率以及match-line耗電量減少了平均為49%，51%，51%。 | zh_TW |
| dc.description.abstract | Content Addressable memory (CAM) is a storage device which is widely implemented in the IP look-up table of a network router due to its high speed searching performance. In IPv6, the IP address will be 128 bits, as a result, the storage size of CAM will be larger in the future. The simulation time is an important factor affecting time-to-market. Using transistor level simulation such as SPICE in the early design stage of CAM will take huge time and delay time-to-market. SystemC is a system level modelling language and simulation platform, it provides better simulation efficiency and ability of hardware software co-design. However SystemC does not provide the function to estimate power consumption for low power algorithm or structure design. In this thesis, we developed a SystemC CAM power estimation tool (SystemC CAM PET) to estimate match-line power of CAM in the early design stage. We construct a new CAM match-line power model to estimate match-line power consumption. We simulated 10 benchmarks of Mibench and compared our SystemC CAM PET simulation results with SPICE simulation results. The simulation time is shorter in average 1654 and error rate of match-line power, search-line and storage cell estimation is average 14.79%, 11.681%, 3.66%. In addition, our SystemC CAM PET is able to calculate the miss rate, data comparison times, input and search data activity of each benchmark for PB-CAM structure. We also proposed a low power improvement example for PB-CAM structure using Gate-Block selection algorithm and verify it by our SystemC CAM PET. The number of data comparisons, miss rate and match-line power consumption are reduced by 49%, 51%, 51% in average. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:01:03Z (GMT). No. of bitstreams: 1 ntu-99-R97922087-1.pdf: 1754767 bytes, checksum: 4ac1c37895fcdf56e248d4dec83b900e (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii Abstract iv List of Figures vii List of Tables viii Chapter 1 Introduction 1 1.1 Concept of Content Addressable Memory 3 1.1.1 Content Addressable Memory 3 1.1.2 Applications of Content Addressable Memory 4 1.1.3 CAM Cell 5 1.1.4 Write Operation of a CAM Cell 6 1.1.5 Read Operation of a CAM Cell 8 1.1.6 Search Operation of a CAM Cell 9 1.1.7 Match-line Structure 11 1.2 Introduction of SystemC 14 Chapter 2 Related Work 16 2.1 Pre-computation Scheme 16 2.1.1 Ones Count Scheme 18 2.1.2 Block-XOR Scheme 18 2.1.3 Gate-Block Selection Algorithm 20 2.2 Noxim 22 2.3 Motivation and Objective 22 Chapter 3 Proposed Approach 24 3.1 CAM Power Model 24 3.1.1 Match-line power model 24 3.1.2 Search-line power model 26 3.1.3 Storage cell array power estimation 26 3.3 Mibench 31 3.4 A low power improvement example 31 3.4.1 Introduction of the Gate-Block Selection Algorithm PB-CAM structure 31 3.4.2 A low power improvement method 32 Chapter 4 Experimental Results 35 4.1 Experimental Environment 35 4.2 Results 36 4.2.1 SystemC CAM PET experimental result 36 4.2.2 A low power improvement method experimental result 38 Chapter 5 Conclusion and Future Work 47 References 49 | |
| dc.language.iso | en | |
| dc.title | SystemC 內容可定址記憶體早期設計驗證的耗電測量工具 | zh_TW |
| dc.title | A SystemC Content Addressable Memory Power Estimation Tool for Early Design Verification | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 許孟超(Mon-Chau, Shie),阮聖彰(Shanq-Jang, Ruan),蔡坤霖(Kun-Lin, Tsai),林振群(JenChiun,Lin) | |
| dc.subject.keyword | 內容可定址記憶體,預先計算,低功率,SystemC,SPICE,電腦輔助設計工具, | zh_TW |
| dc.subject.keyword | content addressable memory (CAM),SystemC,pre-computation,low power,SPICE,computer-aided design tool, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-07-28 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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