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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
| dc.contributor.author | Chun-Hung Liu | en |
| dc.contributor.author | 劉俊宏 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:48:25Z | - |
| dc.date.available | 2010-08-05 | |
| dc.date.copyright | 2010-08-05 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-02 | |
| dc.identifier.citation | [1] 2010 IC/CAD contest. http://cadcontest.ee.ntu.edu.tw/cad10/.
[2] Cadence SoC Encounter. http://www.cadence.com/. [3] IWLS 2005 benchmarks. http://iwls.org/iwls2005/benchmarks.html. [4] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, and Y.-W. Chang, “NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 7, pages 1228–1240, July 2008. [5] J. Cong, G. Luo, J. Wei, and Y. Zhang, “Thermal-aware 3D IC placement via transformation,” in Proceedings of Asia and South Paci c Design Automation Conference, pages 780–785, Yokohama, Japan, January 2007. [6] J. Cong and G. Luo, “A multilevel analytical placement for 3D ICs,” in Proceedings of Asia and South Paci c Design Automation Conference, pages 361–366, Yokohama, Japan, January 2009. [7] J. Cong and G. Luo, “An analytical placer for mixed-size 3D placement,” in Proceedings of International Symposium on Physical Design, pages 61–66, San Francisco, CA, March 2010. [8] X. Y. Dong and Y. Xie, “System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs),” in Proceedings of Asia and South Paci c Design Automation Conference, pages 234–241, Yokohama, Japan, January 2009. [9] S. Dutt, “New faster Kernighan-Lin-type graph-partitioning algorithms,” in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pages 370–377, Santa Clara, CA, November 1993. [10] C. M. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving network partitions,” in Proceedings of ACM/IEEE Design Automation Conference, pages 175–181, January 1982. [11] B. Goplen and S. Sapatnekar, “Placement of 3D ICs with thermal and interlayer via considerations,” in Proceedings of ACM/IEEE Design Automation Conference, pages 626–631, San Diego, CA, June 2007. [12] R. Hentschke, G. Flach, F. Pinto, and R. Reis, “An algorithm for I/O partitioning targeting 3D circuits and its impact on 3D-vias,” in Proceedings of IEEE International Conference on Very Large Scale Integration, pages 128–133, Nice, France, October 2006. [13] D. Hill, “US patent 6,370,673: Method and system for high speed detailed placement of cells within an intergrated circuit design,” 2002. [14] M.-K. Hsu, C.-H. Liu, and Y.-W. Chang, “TSV-aware analytical placement for 3D IC designs,” Technical Report, Industrial Technology Research Institute, Hsinchu, Taiwan, December 2009. [15] A. B. Kahng and Q. Wang, “Implementation and extensibility of an analytic placer,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pages 734–747, May 2005. [16] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel hypergraph partitioning: application in VLSI domain,” in Proceedings of ACM/IEEE Design Automation Conference, pages 526–529, Anaheim, CA, June 1997. [17] G. Karypis and V. Kumar, “Multilevel k-way hypergraph partitioning,” in Proceedings of ACM/IEEE Design Automation Conference, pages 343–348, New Orleans, LA, June 1999. [18] B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” The Bell System Technical Journal, Vol. 49, No. 2, pages 291–307, February 1970. [19] D. H. Kim, K. Athikulwongse, and S. K. Lim, “A study of through-silicon-via impact on the 3D stacked IC layout,” in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pages 674–680, San Jose, CA, November 2009. [20] D. L. Lewis and H.-H. S. Lee, “Testing circuit-partitioned 3D IC designs,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, pages 139–144, May 2009. [21] W. C. Naylor, R. Donelly, and L. Sha, “US patent 6,301,693: Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,” 2001. [22] G.-Y. Pan, H.-K. Kuo, T.-W. Chang, B.-C. Lin, and J.-Y. Jou, “An iterative partition algorithm to minimize area and vertical interconnections for three-dimensional integrated circuits,” in Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2009. [23] D. G. Schweikert, B. W. Kernighan, “A proper model for the partitioning of electrical circuits,” in Proceedings of Design Automation Workshop, pages 57–62, June 1972. [24] P. Spindler, U. Schlichtmann, and F. M. Johannes, “Abacus: Fast legalization of standard cell circuits with minimal movement,” in Proceedings of International Symposium on Physical Design, pages 47–53, Portland, OR, April 2008. [25] T. Yan, Q. Dong, Y. Takashima, and Y. Kajitani, “How does partitioning matter for 3D floorplanning?,” in Proceedings of Great Lakes Symposium on VLSI, pages 73–78, Philadelphia, PA, April 2006. [26] H. Zhou, “Efficient Steiner tree construction based on spanning graphs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 5, pages 704–710, May 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45900 | - |
| dc.description.abstract | 三維積體電路技術需要矽導通孔 (through-silicon vias, TSVs) 來幫助傳輸不同晶片層之間的信號。矽導通孔所佔用的晶片面積會導致三維積體電路的實體設計面臨嚴峻的挑戰。為了準確地評估三維積體電路的製造成本，本篇論文提出一個更精準的成本模型，且比起其他現有的成本模型，此成本模型可以產生更合理且更精準的實驗結果。此外，現今已發表的二維平面電路分割文獻，只專注於減少分割線 (net-cut) 的數量，本論文提出一個多層次且考量矽導通孔的三維積體電路分割演算法，並且提出一個簡易的閘級成本評估流程來評估三維積體電路的閘級成本。此外，本論文也提供了一個三維積體電路的擺置與繞線流程，利用現有的二維擺置器和二維繞線器。流程分為四個階段：(1) 層與層的全域擺置、(2) 矽導通孔的插入和考量矽導通孔的合法化、(3) 層與層的細部擺置、(4) 層與層的繞線。由於標準元件所在的實體晶片層數已在電路分割的階段決定，因此現有的二維擺置器可直接用來擺置標準元件。此外，由於矽導通孔的實體位置也已在矽導通孔插入的階段決定，因此三維繞線可以利用傳統的二維繞線器來實現。實驗結果說明，相對於現今平面電路分割器和三維擺置器的文獻，我們的演算法可以達到最佳的閘級成本與最少的矽導通孔數量。 | zh_TW |
| dc.description.abstract | Through-silicon vias (TSVs) are required for transmitting signals between different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon area occupied by TSVs causes critical challenges to physical design for 3D ICs. To accurately evaluate the cost of 3D ICs, this work presents an enhanced cost model, and experimental results justify that this model is more accurate and reasonable than other existing ones. Besides, unlike most published 2D partitioning works that only minimize the number of net-cuts during partitioning, this thesis proposes a multilevel TSV-aware partitioning algorithm for 3D ICs which considers the area overhead induced by TSVs, and this algorithm helps to evaluate the cost for manufacturing 3D ICs. Moreover, this thesis provides a place-and-route flow of 3D ICs by using a well-known 2D placer and a commercial 2D router. The place-and-route flow consists of four stages: (1) layer-by-layer global placement, (2) TSV insertion and TSV-aware legalization, (3) layer-by-layer detailed placement, and (4) layer-by-layer routing. Since the physical layers of cells are decided during partitioning, an existing 2D placer can be directly applied to place cells layer by layer. Moreover, since the physical positions of TSVs are determined during TSV insertion, 3D routing can be easily accomplished by using a traditional 2D router. Experimental results show that our algorithm can significantly reduce the cost and the TSV count, compared with other partitioning and 3D placement works. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:48:25Z (GMT). No. of bitstreams: 1 ntu-99-R97921024-1.pdf: 2261658 bytes, checksum: c5b300a21d8bfd943d9550e0a34a5687 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Acknowledgements i
Abstract (Chinese) ii Abstract iv List of Figures viii List of Tables x Chapter 1. Introduction 1 1.1 3D IC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.1 Cost Evaluation Works . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.2 Partitioning Works . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.3 Placement for 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 2. Problem Formulation 11 Chapter 3. Algorithm 15 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Enhanced Cost Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Cost Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 Reduced Cost Model . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 Enhanced Cost Model Considering Chip Area . . . . . . . . . . . . 20 vi3.2.4 Enhanced Cost Model Considering the Relationship Among Layers 21 3.3 Cost Evaluation Flow for 3D ICs . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 Multilevel TSV-Aware Partitioning Algorithm for 3D ICs . . . . . 22 3.3.2 Cost Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Place-and-Route Flow of 3D ICs . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1 Layer-by-Layer Global Placement . . . . . . . . . . . . . . . . . . . 29 3.4.2 TSV Insertion and TSV-Aware Legalization . . . . . . . . . . . . . 31 3.4.3 Layer-by-Layer Detailed Placement . . . . . . . . . . . . . . . . . . 35 3.4.4 Layer-by-Layer Routing . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4. Experimental Results 37 4.1 Comparisons of Cost Models . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2 Comparisons of Partitioning Algorithms . . . . . . . . . . . . . . . . . . . 39 4.3 Comparisons of Placement Results . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 5. Conclusions and Future Work 47 Bibliography 49 | |
| dc.language.iso | en | |
| dc.subject | 分割 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 矽導通孔 | zh_TW |
| dc.subject | 閘級成本評估 | zh_TW |
| dc.subject | 3D ICs | en |
| dc.subject | Partition | en |
| dc.subject | Gate-Level Cost Evaluation | en |
| dc.subject | TSVs | en |
| dc.title | 三維積體電路之閘級成本評估 | zh_TW |
| dc.title | Gate-Level Cost Evaluation for Three-Dimensional Integrated Circuits | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊佳玲(Chia-Lin Yang),江介宏(Jie-Hong Jiang),盧奕璋(Yi-Chang Lu) | |
| dc.subject.keyword | 三維積體電路,矽導通孔,閘級成本評估,分割, | zh_TW |
| dc.subject.keyword | 3D ICs,TSVs,Gate-Level Cost Evaluation,Partition, | en |
| dc.relation.page | 52 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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