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標題: | 60-GHz低功耗振幅偏移調變收發機設計與低雜訊放大器線性化技術 60-GHz Low Power ASK Transceiver Design and Linearization of Low Noise Amplifier |
作者: | Wei-Hung Chou 周韋宏 |
指導教授: | 黃天偉 |
關鍵字: | 60-GHz,振幅偏移調變,收發機,低雜訊放大器,線性化, 60-GHz,Amplitude Shift Keying (ASK),Transceiver,Low Noise Amplifier,Linearization, |
出版年 : | 2010 |
學位: | 碩士 |
摘要: | 本論文研究方向著重於應用60-GHz之振幅偏移調變(ASK)收發機設計與低雜訊放大器之線性化技術。
隨著無線通訊技術的發展,較低頻率之頻段使用已經接近飽和,迫使毫米波頻段之設計與應用成為備受關注的研究課題。此外,在傳輸資料量日增月異的情況下,如何實現寬頻的收發機設計以達到高速的資料傳輸也成了重要題目。IEEE 802.15.3C之規範定義了7 GHz的頻寬用來做高速的短距離傳輸使用,使得例如高畫質影片的傳送應用在幾秒內就可以完成。如果想要將此收發機實現在可移動式設備上,功耗與成本絕對是重要考量。因此論文的第一部份,以低功耗及低成本之調變技術為目標,利用互補式金氧半導體(CMOS) 0.13微米製程設計了使用ASK調變技術的發射器與收發機。發射器由一個ASK調變器與使用分佈式主動轉換器之功率放大器組成。在消耗561毫瓦的功耗下,OP1dB為10.8dBm,可以達到超過2Gbps的傳輸速度。收發機則是由ASK調變器、ASK解調器、切換器、中功率放大器所組成,僅消耗154.8毫瓦,OP1dB為-4.7dBm,預期最大傳輸及接收速率可以達到3Gbps。 第二部份探討當使用高頻譜使用效率的調變技術時,元件的非線性問題導致交互調變影響接收訊號解調的正確度,而低雜訊放大器的三階非線性項在低輸入功率時是致使問題發生的主因。因此我們探討與比較目前線性化的技術,並使用修正的導數疊加(Derivative Superposition)方法應用於90nm CMOS製程的低功耗60-GHz低雜訊放大器,藉由並聯一個線性器抵銷三階非線性項提高線性度。放大器在10.8毫瓦的消耗功率下,最高增益11.5dB。而雜訊指數在60 GHz時是5.3 dB,在60.8 GHz到66 GHz的頻率下從4.4 dB至6.3 dB。低輸入功率時可以改善三階項8dB,使IIP3從原來的-5dBm提高至0 dBm。 In this thesis, a 60-GHz ASK Transceiver and a low noise amplifier with built-in linearizer are developed. As the demands for wireless communication technology are growing rapidly in the recent years, the usage of lower frequency band has gradually saturated, and it forces the research of millimeter-wave circuit design to become a hot topic. Furthermore, the transmission data rate has also increased which implies the task of designing the wideband transceiver would be essential. The standard of IEEE 802.15.3c has defined 7-GHz bandwidth to fulfill the high-speed transmission of wireless personal network, which is capable to transmit the high definition video file wirelessly in the few seconds. To realize the transceiver on the mobile devices, power consumption and manufacturing cost are definitely the major concerns. Therefore, in the first part of thesis, we propose the transceiver using the ASK modulation technique which tally with the foregoing purpose of low power consumption and manufacturing cost. They are fabricated by 0.13 μm CMOS technology. The transmitter includes a distributed active transformer (DAT) power amplifier and an ASK modulator. The transmitter OP1dB is 10.8 dBm for 561 mW dc power consumption, and it is expected to transmit the data over 2 Gbps. The transceiver is composed of a ASK modulator, a ASK demodulator, a medium power amplifier, and a traveling-wave type switch. The OP1dB is measured to be -4.7 dBm under mere 154.8 mW power consumption, and the data rate around 3 Gbps is achievable through modulation and demodulation measurement. In the second part, we discuss the nonlinearity problem which may lead to higher bit-error rate (BER) especially with high spectral-efficiency modulation technique. After comparing the existing linearization techniques, we propose a 90nm CMOS technology 60-GHz low power low noise amplifier with modified derivative superposition technique. The linearizer is placed in parallel to the gain stage and has been demonstrated 8-dB IMD3 suppression and 5-dB IIP3 improvement from original -5 dBm to 0 dBm. The peak gain is 11.5 dB and the dc power consumption is 10.8 mW. Besides, noise figure (NF) is 5.3 dB at 60 GHz and ranges from 4.4 dB to 6.3 dB in the interested band. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45678 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
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