請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45539完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪士灝 | |
| dc.contributor.author | Wen-Chang Hsu | en |
| dc.contributor.author | 許文昌 | zh_TW |
| dc.date.accessioned | 2021-06-15T04:25:58Z | - |
| dc.date.available | 2009-09-02 | |
| dc.date.copyright | 2009-09-02 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-20 | |
| dc.identifier.citation | [1] Dinero IV cache simulator, online at:http://www.cs.wisc.edu/~markhill/DineroIV.
[2] T. Austin, E. Larson, and D. Ernst. SimpleScalar: an infrastructure for computer system modeling. Computer, 35(2):59 67, 2002. [3] P. Barham, B. Dragovic, K. Fraser, S. Hand, T. Harris, A. Ho, R. Neugebauer, I. Pratt, and A. War eld. Xen and the art of virtualization. SIGOPS Oper. Syst. Rev., 37(5):164 177, 2003. [4] R. Bedichek. SimNow: fast platform simulation purely in software, robert bedichek. 16th Hot Chips Symp, Aug. 2004. [5] F. Bellard. QEMU, a fast and portable dynamic translator. In Proceedings of the annual conference on USENIX Annual Technical Conference, pages 41 41, Anaheim, CA, 2005. USENIX Association. [6] M. V. Biesbrouck, L. Eeckhout, and B. Calder. E cient sampling startup for sampled processor simulation. In High Performance Embedded Architectures and Compilers, pages 47 67. 2005. [7] P. Bjuréus and A. Jantsch. Performance analysis with con dence intervals for embedded software processes. In Proceedings of the 14th international symposium on Systems synthesis, pages 45 50, Montréal, P.Q., Canada, 2001. ACM. [8] S. Browne, C. Deane, G. Ho, and P. Mucci. PAPI: a portable interface to hardware performance counters. In Proceedings of Department of Defense HPCMP Users Group Conference, Monterey, California, 1999. [9] A. Falcon, P. Faraboschi, and D. Ortega. Combining simulation and virtualization through dynamic sampling. In 2007 IEEE International Symposium on Performance Analysis of Systems & Software, pages 72 83, San Jose, CA, USA, 2007. [10] J. Fenlason and R. Stallman. GNU gprof. GNU Free Software Foundation, 1998. [11] S. Fischmeister and P. Lam. On Time-Aware instrumentation of programs. [12] S. B. Furber. ARM system-on-chip architecture. Addison-Wesley Professional, 2000. [13] P. Giusto, G. Martin, and E. Harcourt. Reliable estimation of execution time of embedded software. In Proceedings of the conference on Design, automation and test in Europe, pages 580 589, Munich, Germany, 2001. IEEE Press. [14] google. android opensource project, 2007. [15] M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. MiBench: a free, commercially representative embedded benchmark suite. In Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, pages 3 14, 2001. [16] K. Karuri, M. A. A. Faruque, S. Kraemer, R. Leupers, G. Ascheid, and H. Meyr. Fine-grained application source code pro ling for ASIP design. In Proceedings of the 42nd annual conference on Design automation, pages 329 334, Anaheim, California, USA, 2005. ACM. [17] T. L. Lai and H. W. Robbins. Strong consistency of least squares estimates in multiple regression. Proceedings of the National Academy of Sciences USA, 75(7), 1978. [18] M. Lazarescu, J. Bammi, E. Harcourt, L. Lavagno, and M. Lajolo. Compilationbased software performance estimation for system level design. In High-Level Design Validation and Test Workshop, 2000. Proceedings. IEEE International , pages 167 172, 2000. [19] A. R. M. Ltdl. RealView ARMulator. [20] L. McVoy and S. Graphics. lmbench: Portable tools for performance analysis. [21] S. Microsystem. VirtualBox. [22] N. Nethercote and J. Seward. Valgrind: a framework for heavyweight dynamic binary instrumentation. In Proceedings of the 2007 PLDI conference, volume 42, page 89�100, 2007. [23] B. Netherton. DTrace. In Solaris 10 Workshop, 2005. [24] M. S. Oyamada, F. Zschornack, and F. R. Wagner. Applying neural networks to performance estimation of embedded software. J. Syst. Archit., 54(1-2):224 240, 2008. [25] E. Perelman, G. Hamerly, M. V. Biesbrouck, T. Sherwood, and B. Calder. Using SimPoint for accurate and e cient simulation. In Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 318 319, San Diego, CA, USA, 2003. ACM. [26] V. J. Reddi, A. Settle, D. A. Connors, and R. S. Cohn. Pin: A binary instrumentation tool for computer architecture research and education. In Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture, 2004. [27] F. Stappert. WCET benchmarks. 2003. [28] I. VMware. VMware. Inc., VMware products, VMware, Inc., Palo Alto, CA, USA (2008)< http://www. vmware. com/products/>[accessed 01.03. 08], 2008. [29] D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMsim: a memory system simulator. ACM SIGARCH Computer Architec- ture News, 33(4):100�107, 2005. [30] R. E. Wunderlich, T. F. Wenisch, B. Falsa , and J. C. Hoe. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling. In Proceedings of the 30th annual international symposium on Computer architecture, pages 84 97, San Diego, California, 2003. ACM. [31] M. Yourst. PTLsim: a cycle accurate full system x86-64 microarchitectural simulator. In Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on, pages 23 34, 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45539 | - |
| dc.description.abstract | 本論文主要是在虛擬平台上建立一個軟體剖析(profiling)機制來協助在嵌
入式系統上的軟體開發工作，此機制主要是建立在QEMU 這個開放原始碼的模擬器 上。QEMU 模擬器廣泛被使用在開發嵌入式軟體的計畫中，如包含在Android 軟體 開發工具組中用來作為Android 開放原始碼平台中之虛擬平台，用以加速並協助 Android 系統上的軟體開發。然而，在現有的QEMU 設計中並沒有估量軟體執行時 間的相關機制，因此我們嘗試在該虛擬平台上建立一套效能分析的架構，我們的 目標是提供快速並且準確的時間評估模型來幫助程式設計師在系統開發的早期估 測程式效能。我們的實驗展示數個不同的時間模型，提供較高精準度的模型需要 較長的模擬時間，使用者可以跟據自己的需求，在模擬時間與準確率之間折衷選 擇。 | zh_TW |
| dc.description.abstract | In this paper, we present a performance analysis framework to support application
development on heterogeneous multicore systems with virtual platforms. Our work is based on the open source QEMU simulator which has been widely used to develop software on embedded systems and was included in the Android Software Development Kit. However, to support the software development on multicore platfroms, timing information is critical and thus we attempt to build virtual platforms with the capacity of performance evaluation. Our goal is to provide a framework that gives quick, accurate timing estimation to help multicore application development during early design phases. In this paper, we discuss the construction of various timing models for our virtual platform to simulate program execution. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T04:25:58Z (GMT). No. of bitstreams: 1 ntu-98-R96922119-1.pdf: 4222235 bytes, checksum: d615d40395ffc39629b385062134fdc9 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Acknowledgements ii
Abstract (Chinese) iii Abstract iv List of Tables vii List of Figures viii 1 Introduction 1 1.1 Scenarios of Using Virtualization Techniques . . . . . . . . . . . . . 2 1.2 Approaches for Proling . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Proling with a Virtual Platform . . . . . . . . . . . . . . . . . . . . 5 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Background and Related Work 7 2.1 Cycle-Accurate Simulation . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Functional Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Proling Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Performance Prediction with simplied Hardware Models . . . . . . . 12 2.5 Virtual Platform with Timing Models . . . . . . . . . . . . . . . . . . 14 3 Implementation of Timing Models in QEMU 15 3.1 QEMU Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Overview of our Virtual Platform . . . . . . . . . . . . . . . . . . . . 17 3.3 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 Regression Timing Model A, B and C . . . . . . . . . . . . . . 19 3.3.2 Cache Simulation for Model C and Datasheet model . . . . . . 20 3.3.3 Datasheet Model . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.4 OS Scheduler Inuence . . . . . . . . . . . . . . . . . . . . . . 21 4 Experiment Results 24 4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Experiment Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.1 Results and Discussions for Model A and B . . . . . . . . . . 27 4.2.2 Model C and Datasheet Model . . . . . . . . . . . . . . . . . . 31 5 Conclusion and Future Work 38 Bibliography 40 | |
| dc.language.iso | en | |
| dc.subject | 效能分析 | zh_TW |
| dc.subject | 虛擬化技術 | zh_TW |
| dc.subject | 嵌入式系統 | zh_TW |
| dc.subject | performance analysis | en |
| dc.subject | virtual platform | en |
| dc.subject | embedded systems | en |
| dc.title | 以虛擬平台進行快速且非侵入式地解析應用程式效能 | zh_TW |
| dc.title | Fast and Non-intrusive Profiling of Application
Performance with a Virtual Platform | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭大維,施吉昇,王勝德 | |
| dc.subject.keyword | 虛擬化技術,嵌入式系統,效能分析, | zh_TW |
| dc.subject.keyword | virtual platform,embedded systems,performance analysis, | en |
| dc.relation.page | 44 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 4.12 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。