Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45488
Title: | 24 GHz低雜訊放大器之研製 Design of 24 GHz Low-Noise Amplifier |
Authors: | Bo-Chan Chen 陳柏誠 |
Advisor: | 江簡富(Jean-Fu Kiang) |
Keyword: | 24GHz,LNA,閘極偏壓電路,溫度,製程變異, 24 GHz,LNA,gate-bias circuit,temperature,process change, |
Publication Year : | 2009 |
Degree: | 碩士 |
Abstract: | 一24 GHz低雜訊放大器以CMOS 0.18 um製程來設計並實現,此低雜訊放大器在24 GHz具有15.9 dB的增益及3.3 dB的雜訊指數,P1dB與IIP3分別為-0.91 dBm及-11.7 dBm。此低雜訊放大器在1.8伏特的電源供應下,共消耗21.4 mA的電流及38.5 mW的功率。
一具有閘極偏壓電路的24 GHz低雜訊放大器以CMOS 0.18 um製程來設計並實現,此低雜訊放大器在24 GHz具有12.7 dB的增益及3.77 dB的雜訊指數,採用電流重複利用的架構來降低功耗,在1.8伏特的電源供應下消耗28.9 mW的功率;所提出的閘極偏壓電路,可以使增益因為溫度差異所造成的變動範圍從4.53 dB減少為2.85 dB,使增益因為製程變異所造成的變動範圍從5 dB減少為3.96 dB。 A 24 GHz three-stage low-noise amplifier is designed and implemented in a 0.18 μm CMOS technology. The LNA has a gain of 15.9 dB and minimum noise figure of 3.3 dB at 24 GHz. The input 1-dB compression point (P1dB) and third order intercept point (IIP3) are −11.7 dBm and −0.91 dBm, respectively. This LNA consumes a total current of 21.4 mA and power of 38.5 mW on a 1.8 V power supply. A 24 GHz low-noise amplifier with gate-bias circuit is designed and implemented using a 0.18 μm CMOS technology. The LNA has a gain of 12.7 dB and minimum noise figure of 3.77 dB at 24 GHz. It adopts a current-reuse technique to reduce the power consumption to 28.9 mW at 1.8 V power supply. The proposed bias circuit reduces the gain variation range due to temperature change from 4.53 dB to 2.85 dB, and that due to process change from 5 dB to 3.96 dB. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45488 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電信工程學研究所 |
Files in This Item:
File | Size | Format | |
---|---|---|---|
ntu-98-1.pdf Restricted Access | 2.47 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.