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標題: | 深次微米CMOS製程之時脈產生器的設計與實作 Design and Implementation of Clock Generators in Nanoscale CMOS Processes |
作者: | Jung-Yu Chang 張鎔諭 |
指導教授: | 劉深淵 |
關鍵字: | 鎖相迴路,延遲鎖定迴路,漏流補償,突波雜訊, Phase-locked loop,delay-locked loop,leakage compensation,spur, |
出版年 : | 2010 |
學位: | 博士 |
摘要: | 隨著CMOS製程的進步,對高速的通訊系統的需求也逐漸增加。由於時脈產生器往往決定了系統的速度以及效能,因此在一個通訊系統中它扮演了一個相當重要的角色。然而在90nm或65nm製程中,漏流問題會嚴重地影響時脈產生器的效能,本論文的目的即在解決時脈產生器在深次微米製程下所遇到的問題。
鎖相迴路和延遲鎖定迴路被廣泛地應用在時脈產生器。鎖相迴路通常適用於高速應用,然而由於它的迴路濾波器面積較大,因此很難去實現一個完全整合的鎖相迴路;雖然利用MOS電容可以有效減小鎖相迴路的面積,然而在深次微米製程下,MOS電容所產生的漏流將會使鎖相迴路的效能降低;此外,通道長度調變所產生的突波雜訊問題也是需要去注意的。相對於鎖相迴路,延遲鎖定迴路通常有較好的抖動效能及較小的面積,然而壓控延遲線的有限頻寬往往限制住延遲鎖定迴路的操作頻率。 在本論文中,首先提出了兩個漏流補償電路,在第一個電路中,藉由偵測參考訊號和迴授時脈的相位差,將會產生相對應的補償電流;然而在補償完成後的開迴路特性,使得第一個電路無法去補償因溫度或電壓源變化所產生的漏流,第二個漏流補償電路即在解決這個問題,它可以在溫度或電壓源變化時持續地去補償MOS電容所產生的漏流。接著介紹一個降低突波雜訊的電路,利用將突波雜訊的頻率重新分配的概念,可以有效地降低突波雜訊。 最後提出了一個操作在20GHz的延遲鎖定迴路,利用注入鎖定除頻器,壓控延遲線的頻寬限制將可以被降低,同時也提出了一個適用於高速應用的起動電路。 在深次微米下,鎖相迴路的漏流問題和延遲鎖定迴路的頻寬限制使得時脈產生器的設計變得困難,本論文提出了四種方案來解決這些問題。 With the progress of the CMOS technologies, the demand of high-speed communication system grows gradually. The most important part of the communication system is clocking system, which directly determines the speed and system performance. However, the leakage problem in 90nm or 65nm processes will degrade the performance of the clock systems, and the subject of this dissertation is to solve the problems of clock generators in nanoscale processes. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed for the clock generation. PLLs are usually used in the high speed applications due to their clock multiplication architecture, but it is hard to integrate a PLL on a chip because the area of loop filter is large. To reduce the physical size of a PLL, the capacitor in loop filter is usually realized by the MOS capacitor. However, in nanoscale processes, the large leakage current due to oxide tunneling current will degrade the performance of a PLL seriously, and the severe channel length modulation will produce large reference spur. These problems must be taken into account when the clock generators are implemented in nanoscale processes. Compared with PLLs, DLLs usually have better jitter performance and small chip area. However, the limited bandwidth of the voltage-controlled delay line (VCDL) makes the DLLs hard to operate at high frequency. . In this dissertation, two leakage compensated circuits are proposed to solve the leakage current caused by MOS capacitor. By detecting the phase error between the reference signal and feedback clock, the corresponding compensated current can be produced in first work. However, the open loop structure after compensation makes that the first work can’t track the variations of temperature or supply voltage. The background compensation has been proposed to solve this problem. It can keep compensation when the temperature or supply voltage changes. Then a spur suppression technique is presented to solve the spur problem caused by subthreshold leakage or CP mismatch. By redistributing the frequency of spur, the amplitude of reference spur can be reduced. Finally, a 20GHz DLL is presented. Using the injection locked frequency divider, the speed limitation of the VCDL can be relaxed. Moreover, a new start-up circuit is also proposed for high frequency application. In nanoscale processes, the leakage problems in PLLs and limited bandwidth in DLLs make the design of clock generators hardly. This dissertation proposes four solutions to solve these problems. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45209 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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