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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
dc.contributor.author | Chun-Wei Chen | en |
dc.contributor.author | 陳峻偉 | zh_TW |
dc.date.accessioned | 2021-06-15T03:58:54Z | - |
dc.date.available | 2011-07-05 | |
dc.date.copyright | 2010-07-05 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-04-27 | |
dc.identifier.citation | References
[1] Document Object Model, http://www.w3.org/dom/. [2] Simple API for XML, http://www.saxproject.org/. [3] UTF-8 standard: RFC3629, http://tools.ietf.org/html/rfc3629. [4] VTD-XML:The Future of XML Processing, http://vtd-xml.sourceforge.net/. [5] Wei Lu, Kenneth Chiu, Yinfei Pan, A Parallel Approach to XML Parsing, Grid Computing Conference, 2006. [6] C.-H. Chen, Hardware Accelerated XML Parser for Virtual Token Descriptor, National Taiwan University, 2009. [7] J. Zhang. Process XML on a chip. In CommsdDesign Magazine, 2005. [8] Wei Zhang and Robert A. van Engelen, An Adaptive XML Parser for Developing High-Performance Web Services, IEEE International Conference, 2008. [9] W.-S. Chang, A XPATH Processing Engine for Virtual Token Descriptor, 2009. [10] Kai Ning Luoming Meng, Design and Implementation of the DTD-based XML Parser, ICCT, 2003. [11] Yinfei Pan, Ying Zhang, Kenneth Chiu, Wei Lu, Parallel XML Parsing Using Meta-DFAs, IEEE International Conference, 2007. [12] Fadi E. and Dan I., SCBXP: AN EFFICIENT HARDWARE-BASED XML PARSING TECHNIQUE, IEEE International Conference, 2009. [13] Yinfei Pan, Ying Zhang, and Kenneth Chiu, Simultaneous Transducers for Data-Parallel XML Parsing, IEEE International Conference, 2008. [14] Tak Cheung Lam, Jyh-Charn Liu, Jianxun Jason Ding, XML Document Parsing: Operational and Performance Characteristics, IEEE Computer Society, 2008. [15] KRISHNAMOORTHY, REMYA. Hardware Implementation of an XML Parser, North Carolina State University, 2008. [16] Margaret G. Kostoulas, Morris Matsa, Noah Mendelsohn, Eric Perkins, Abraham Heifets, XML Screamer: An Integrated Approach to High Performance XML Parsing, International World Wide Web Conference Committee, 2006. [17] Relax NG specification, http://relaxng.org/spec-20011203.html, 2001. [18] J. van Lunteren et al., XML Accelerator Engine, Int’l Workshop High Performance XML Processing, 2004, www.zurich.ibm.com/~jvl/xml2004.pdf. [19] Apache Foundation, Xerces XML Parser, http://xerces.apache.org. [20] ML505/ML506/ML507 Evaluation Platform User Guide, Xilinx, Inc, 2008. [21] ML505/ML506/ML507Tutorial Getting Started, Xilinx, Inc, 2008. [22] Embedded Development Kit 10.1, Xilinx, Inc, 2008. [23] PLBV46 Master Single, Xilinx, Inc, 2008. [24] Block Memory Generator v2.8 User Guide, Xilinx, Inc, 2008. [25] FIFO Generator v4.4 User Guide, Xilinx, Inc, 2008. [26] Multi-Port Memory Controller v4.02.a, Xilinx, Inc, 2008. [27] PLBV46_SLAVE v1.01b, Xilinx, Inc, 2008. [28] PLBV46 Master Single v1.00a, Xilinx, Inc, 2008. [29] PLBV46 Master Burst v1.01a, Xilinx, Inc, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44939 | - |
dc.description.abstract | 可擴展標記語言(XML)從1995年誕生,是一種跨平台通用的標記語言。利用其可擴展的特性,使用者可以自訂各式各樣的文件,以方便各類型的應用程式進行資料儲存以及資訊交換。目前可擴展標記語言已經被廣泛的使用在我們的生活中,舉凡網際網路之資訊交換、不同電腦系統之間文件格式的轉換以及各類型應用程式之間的資訊傳遞…等,都可以找到可擴展標記語言的應用。為了讓電腦系統更有效率地處理大量以可擴展標記語言為主的文件,已經有許多處理可擴展標記語言的方法被提出來。在這些旣有的方法中,絕大多數還是以軟體的實作為主。雖然軟體可以輕鬆的達成任務,但卻會使得CPU的負荷過重,進而導致系統的整體效能降低。少數用硬體加速的研究也只是將軟體的演算法實作在硬體上,有些實作為了減少設計的複雜度,直接忽略語法檢查的部份,甚至沒有考慮UTF-8編碼的問題,只有簡單地產生後續處理所需的資訊。為了改善既有的設計方式、降低處理器的負擔並且更有效率地處理可擴展標記語言,我們提出一種應用於可擴展標記語言之以抽象化分類表為目標輸出並具備語法檢查之硬體加速器並提供一個完整的驗證與測試平台供後續研究使用。抽象化分類表為一種針對可擴展標記語言設計之全新的剖析方法,透過這個抽象化分類表,使得可擴展標記語言的後續處理更有效率。在相同的平台上,我們的硬體加速器每秒可達206 MB,超出軟體20倍以上的效能。 | zh_TW |
dc.description.abstract | XML (Extensible Markup Language) is a cross-platform markup language. It has been used on lots of most common applications in our computer system because of the extension and user customization features. In order to parse XML documents efficiently, much research has been done to accelerate the processing of XML documents or messages. The hardware-accelerated approach is becoming important due to a higher performance is getting expected. Current hardware platforms for processing XML documents lack the capability of well-formed checking for XML documents because of complication. To improve existing design methods, lower the CPU load and process XML efficiently, we present a hardware accelerated XML parser with well-formed checker by using the abstract classification table. The approach provides a testing and verification platform for XML processing. Abstract classification table is an emerging indexing technique to represent the hierarchical structure of XML documents and can accelerate XML processing. In our platform, the hardware accelerator can parse XML documents at 206 Mbps and provide a Giga bit level throughput. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T03:58:54Z (GMT). No. of bitstreams: 1 ntu-99-R97921027-1.pdf: 2331179 bytes, checksum: b362610553f4ea48d6a56d624c2a6ea4 (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii Abstract v Chapter 1 Introduction 1 1.1 XML Introduction 1 1.2 Contributions 3 1.3 Thesis Organization 4 Chapter 2 Related Work 6 2.1 Software Approach 6 2.2 Hardware Approach 7 Chapter 3 Design Considerations 10 3.1 UTF-8 10 3.2 Abstract Classification Table 11 3.3 Well-Formed Checker 12 3.3.1 XML Declaration 13 3.3.2 Comment 14 3.3.3 Processing Instructions 15 3.3.4 CDATA Sections 15 3.3.5 DOCTYPE Sections 16 3.3.6 Element Tags 17 3.3.7 Attributes 19 3.3.8 Characters 20 3.4 XML ACT Parser 21 3.5 Module Pipeline 23 3.6 Finite Automata 24 3.7 Parallelism 24 3.8 HW/SW Co-Design 25 Chapter 4 System Architecture 27 4.1 System Architecture 27 4.2 Data Access Block 28 4.2.1 Memory Fetcher 29 4.2.2 Memory Write Back 32 4.2.3 FIFO Fetcher 36 4.2.4 FIFO Merger 37 4.3 Well-Formed Checker 39 4.3.1 XML declaration 42 4.3.2 Comment 43 4.3.3 Processing Instructions 44 4.3.4 CDATA Sections 44 4.3.5 DOCTYPE Sections 45 4.3.6 Element Tags 46 4.3.7 Attributes 47 4.3.8 Characters 47 4.4 XML ACT Parser 48 4.5 XML Parser Halting Mechanism 57 4.6 HW/SW Co-Design Testing 58 Chapter 5 Experimental Results 64 5.1 FPGA Development Board 64 5.2 Integrated Development Environment 65 5.3 Functional Verification 66 5.4 Synthesis Result 70 5.5 System Performance 72 Chapter 6 Conclusions 77 Chapter 7 Future Work 79 References 81 | |
dc.language.iso | zh-TW | |
dc.title | 整合可擴展標記語言語法檢查及以抽象化分類表為目標輸出之硬體加速器 | zh_TW |
dc.title | Hardware Accelerated XML Parsers with Well Form Checkers and Abstract Classification Tables | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 王凡(Farn Wang),洪士灝,鄭振牟(Chen-Mou Cheng) | |
dc.subject.keyword | 可擴展標記語言,抽象化分類表,虛擬標記描述子,萬國碼, | zh_TW |
dc.subject.keyword | XML,ACT,VTD,UTF-8, | en |
dc.relation.page | 83 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2010-04-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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