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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 光電工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44496
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor黃建璋(Jian-Jang Huang)
dc.contributor.authorKuang-Chung Liuen
dc.contributor.author劉光中zh_TW
dc.date.accessioned2021-06-15T03:01:10Z-
dc.date.available2009-08-03
dc.date.copyright2009-08-03
dc.date.issued2009
dc.date.submitted2009-07-31
dc.identifier.citation[1] Donald A. Neamen, “Semiconductor Physics and Devices 3rd”, McGraw Hill, p.486–495.
[2] A. C. Tickle, “Thin-Film Transistors”. New York: John Wily and Sons, 1969.
[3] Jai Il Ryu , Young Jin Choi , In Keun Woo , Byeong Chun Lim , Jin Jang, “High performance a-Si TFT with ITO/n+ ohmic layer using a Ni-silicide”, Journal of Non-Crystalline Solids, 2000.
[4] Byung Chul Ahn, Jeong Hyun Kim, Dong Gil Kim, Byeong Yeon Moon, Kyung Ha Lee, Soon Sung Yoo, Min Koo Han and Jin Jang, “Fabrication of high performance APCVD a-Si TFT using ion doping”, Journal of Non-Crystalline Solids, 1993.
[5] A Comparison of the Performance and Reliability of Wet-Etched and Dry-Etched a-Si:H TFTs”, IEEE transactions on electron devices, 1998.
[6] Chi-Wen Chen, Ting-Chang Chang, Po-Tsun Liu, Hau-Yan Lu, Kao-Cheng Wang, Chen-Shuo Huang, Chia-Chun Ling, and Tesung-Yuen Tseng, “High-Performance Hydrogenated Amorphous-Si TFT for AMLCD and AMOLED Applications”, IEEE electron device letters, 2005.
[7] Chia-Pin Lin, Bing-Yue Tsui, Ming-Jui Yang, Ruei-Hao Huang, and Chao-Hsin Chien, “High-Performance Poly-Silicon TFTs Using HfO2 Gate Dielectric”, IEEE electron device letters, 2006.
[8] S. J. Pearton, D. P. Norton, K. Ip, Y. W. Heo, and T. Steiner, “Recent advances in processing of ZnO”, Journal of Vacuum Science and Technology, May/June, 2004.
[9] Tsay, C.Y., Cheng, H.C., Wang, M.C., Lee, P.Y., Chen, C.F., and Lin, C.K., Surface and Coatings Technology, 202(4-7), Dec 15 2007, pp. 1323-1328.
[10] Dehuff, N. L., Kettenring, E. S., Hong, D., Chiang, H. Q., Wager, J. F., Hoffman, R. L., Park, C.-H., and Keszler, D. A., J. Appl. Phys, 97, 2005, pp. 064505.
[11] Yaglioglu, B., Yeom, H.Y., Beresford, R., and Paine, D.C., Appl. Phys. Lett., 89(6), 2006, pp. 062103.
[12] C.C. Liu, Y.S. Chen and J.J. Huang, “High-performance ZnO thin-film transistors fabricated at low temperature on glass substrates”, Electronics letters, 2006.
[13] Master thesis, Rick E. Presley, “Transparent electronics: thin-film transistors and integrated circuits”, Chapter 4, Oregon State University, 2006.
[14] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”, Nature, 2004.
[15] N. L. Dehuff, E. S. Kettenring, D. Hong, H. Q. Chiang, J. F. Wager, R. L. Hoffman, C.-H. Park, and D. A. Keszler, “Transparent thin-film transistors with zinc indium oxide channel layer,” Journal of Applied Physics, 2005.
[16] G. F. Boesen and J. E. Jacobs, “ZnO Field-Effect Transistor”, Proceeding Letters, IEEE, 1968.
[17] P. F. Carcia, R. S. McLean, M. H. Reily, and G. Nunes, “Transparent ZnO thin-film transistor fabricated by rf magnetron sputtering”, Applied Physics Letters, 2003.
[18] J. Nishii, F. M. Hossain, S. Takagi, T. Aita, K. Saikusa, Y. Ohmaki, I. Ohkubo, S. Kishimoto, A. ira Ohtomo, T. Fukumura, F. Matsukura, Y. Ohno, H. Koinuma, A. H. Ohno, and M. Kawasaki, “High mobility thin film transistors with transparent ZnO channels”, Japanese Journal of Applied Physics, 2003.
[19] S. Masuda, K. Kitamura, Y. Okumura, S. Miyatake, H. Tabata, and T. Kawai, “Transparent thin film transistors using ZnO as an active channel layer and their electrical properties”, Japanese Journal of Applied Physics, 2003.
[20] R. L. Hoffman, B. J. Norris, and J. F. Wager, “ZnO-based transparent thin-film transistors”, Applied Physics Letters, 2003.
[21] B. J. Norris, J. Anderson, J. F. Wager, and D. A. Keszler, “Spin-coated zinc oxide transparent transistors”, Journal of Physics D: Applied Physics, 2003.
[22] Y. Kwon, Y. Li, Y. W. Heo, M. Jones, P. H. Holloway, D. P. Norton, Z. V. Park, and S. Li, “Enhancement-mode thin-film field-effect transistor using phosphorus doped (Zn,Mg)O channel', Applied Physics Letters, 2004.
[23] M. W. J. Prins, K.-O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolfd, “A ferroelectric transparent thin-film transistor”, Applied Physics Letters, 1996.
[24] H. Q. Chiang, J. F. Wager, R. L. Hoffman, J. Jeong, and D. A. Keszler, “High mobility transparent thin-film transistors with amorphous zinc tin oxide channel layer”, Applied Physics Letters, 2005.
[25] E. Fred Schubert, “Delta-doping of semiconductors”, Chapter 1, Cambrige University Press.
[26] 莊達人編, “VLSI製造技術”, 高立, 2004.
[27] J A Venables, G D T Spiller and M Hanbucken, “Nucleation and growth of thin films”, Reports on Progress in Physics, 1984.
[28] http://www.ajaint.com/whatis.htm
[29] http://www.eeel.nist.gov/812/meas.htm
[30] J.H. Kim, B.D. Ahn, C.H. Lee, K.A. Jeon, H.S. Kang, and S.Y. Lee, “Effect of rapid thermal annealing on electrical and opsical properties of Ga doped ZnO films prepared at room temperature”, Journal of Applied Physics, 2006.
[31] T. Yamada, A. Miyake, H. Makino, N. Yamamoto, and T. Yamamoto, “Effect on thermal annealing on electrical properties of transparent conductive Ga-doped ZnO films prepared by ion-plating using direct-current arc discharge”, Thin Solid Films, 2009.
[32] C.C. Liu, M.L. Wu, K.C. Liu, S.H. Hsiao, Y.S. Chen, G.R. Lin, and J.J. Huang, “Transparent ZnO Thin-Film Transistors on Glass and Plastic Substrates Using Post-Sputtering Oxygen Passivation”, Journal of Display Technology, Vol. 5, No. 6, June 2009.
[33] Dieter K. Schroder, “Semiconductor Material and Device Characterization Third Edition”, p. 207, A. JOHN WILEY & SONS, INC., 2006
[34] Farque M. Hossain, J. Nishii, S. Takagi, A. Ohtomo, and T. Fukumura, “Modeling and simulation of polycrystalline ZnO thin-film transistors”, Journal of Applied Physics, VOL. 94, NUM. 12, 2003.
[35] Andrew C. G. Wood, Anthony G. O’Neill, Peter J. Phillips, Robin G. Biswas, Terry E. Whall, and Evan H. C. Parker, IEEE TRANSACTIONS ON ELECTRON DEVICES, WOL. 40, NO. 1, JANUARY 1993 157.
[36] Andrew C. G. Wood, Anthony G. O’Neill, Mat. Res. Soc. Symp. Proc., vol. 220, p. 465, 1991.
[37] Kenji Noda, Toru Tatsumi, Tetsuya Uchida, Ken Nakajima, Hidenobu Miyamoto, and Chenming Hu, “IEEE TRANSACTIONS ON ELECTRON DEVICES”, WOL. 40, NO. 4, APRIL 1998 809.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44496-
dc.description.abstract薄膜電晶體長久以來在液晶顯示技術上扮演著重要的角色,目前顯示技術上的發展趨勢為製作出高透光度的薄膜電晶體陣列,以提高背光使用效率。氧化鋅材料擁有寬能隙、高透光度、高載子遷移率以及可使用射頻磁控濺鍍法低溫沉積等優點,且具有潛力製作薄膜電晶體於塑膠等軟性基板上,以實現可撓性顯示器以及可撓性電路的夢想。
然而在近年來的研究中,氧化鋅薄膜電晶體依舊擁有著一些缺點,像是低工作電流、材料穩定性不足等缺點,限制其在業商業應用上的發展。因此,我們提出了使用新材料,以鎵參雜氧化鋅 (氧化鋅鎵) 製作薄膜電晶體,氧化鋅鎵擁有高載子濃度以及高穩定性,改善了工作電流同時提升元件穩定度,然而元件結構需要改變來適應氧化鋅鎵。在這裡我們試驗了不同通道層厚度以及閘極電極長度的氧化鋅鎵薄膜電晶體,並提出一套模型來解釋其物理現象。成功分析氧化鋅以及氧化鋅鎵薄膜電晶體各自最適合的元件結構,也分別展示了在此最適元件結構下,氧化鋅以及氧化鋅鎵薄膜電晶體各自優異的電特性表現。
此外,為了更進一步提高薄膜電晶體的工作電流以及反應速率,我們製作了世界上第一個可在通道層形成二維電子雲(2DEG)結構的脈衝參雜薄膜電晶體(Delta-doped TFT),並提出模型加以說明工作原理。與本實驗室先前所從事之研究相比,此薄膜電晶體成功提高工作電流,提升開關率(On/Off ratio),並證實可藉由通道參雜結構改變,進一步控制元件之臨界電壓(Threshold voltage)。我們相信以此結構製作之薄膜電晶體擁有世界上屬一屬二的優秀電特性。
zh_TW
dc.description.abstractThin-film transistors (TFTs) have been playing an important role in the LCD display industry. The recent trend of TFTs is the transparent pixel, which can be fulfilled by using zinc oxide (ZnO) as the active layer. ZnO is the material with properties of wide bandgap, high mobility, and easy deposition by RF sputtering at room temperature.
But ZnO also has some drawbacks like the low operating current level and the stability problem. We introduce the gallium doped zinc oxide (GZO) as the active layer. GZO does solve the drawbacks of ZnO above but new problems arisen. We have tried many channel thicknesses and gate sizes of ZnO and GZO TFTs in order to find the best structures of each kind of TFTs. We have successfully explained the structure differences of TFTs by use of a model.
We have also fabricated the delta-doped TFTs so as to further improving of current level and response time. A model has been showed to explain the operation of devices by forming a 2-dimentional electron gas (2DEG) structure in the channel layer successfully, and the controllable threshold voltage is also proved by varying the composition of the delta-doping layer. The result of our delta-doped TFTs is much better than the previous work in our lab, and is believed to be one of the best ZnO-based TFT performances in the world.
en
dc.description.provenanceMade available in DSpace on 2021-06-15T03:01:10Z (GMT). No. of bitstreams: 1
ntu-98-R96941002-1.pdf: 2722086 bytes, checksum: 874ffbf0b52dd1fc3159cf73dadef40d (MD5)
Previous issue date: 2009
en
dc.description.tableofcontentsAbstract………………………………………………………………ii
中文摘要………………………………………………………………iii
Chapter 1 Introduction……………………………………………1
Chapter 1 References……………………………………………4
Chapter 2 Literature Review and Theory…………………5
2.1 Transistors…………………………………………………5
2.1.1 Working principle of field effect transistors………5
2.1.2 Operation of thin film transistors…………………10
2.1.3 Development of ZnO and GZO TFTs…..................13
2.2 Semiconductors Delta-doping Theory……………………..19
2.3 RF Magnetron Sputtering…………………………………….21
Chapter 2 References…………………………………………..22
Chapter 3 Fabrication of ZnO-based TFTs on a Glass Substrate……………………………………………………………26
3.1 Hall measurement of materials………………………….26
3.2 Fabrication process of ZnO TFTs……………………….30
3.3 Fabrication process of GZO TFTs…………………………33
3.4 Fabrication process of ZnO/GZO delta-doped TFTs……35
Chapter 3 References…………………………………………..37

Chapter 4 Gate Length Effect on TFT Electrical
Properties…………………………………………………………38
4.1 Electrical Properties of TFTs with Different Channel Thickness………………………………………………………..38
4.1.1 Structure of GZO TFTs with Different Channel Thickness………………………………………………………..38
4.1.2 Electrical Properties of GZO TFTs with Different Channel Thicknesses……………………………………………..39
4.2 Electrical Properties of TFTs with Different Gate Lengths……………………………………………………………….45
4.2.1 Structures of ZnO TFTs and GZO TFTs………………..45
4.2.2 Electrical Properties of ZnO and GZO TFTs with Different Gate Lengths………………………………………….47
4.3 Discussion on Carrier Modulation Induced by Gate and Drain Electrodes ……………………………………………55
4.3.1 Channel Resistance Model of TFTs……………….55
4.3.2 Channel Energy Band Bending Model of TFTs……57
Chapter 4 References…………………………………………65
Chapter 5 Characterizations of Delta-doped TFTs………66
5.1 Electrical Properties of delta-doped TFTs …………66
5.1.1 Structures of various delta-doped TFTs……………66
5.1.2 Comparison of delta-doped TFTs with various GZO layer depths………………………………………………………………68
5.2 Carrier Transport Behaviors of Delta-doped TFTs…74
5.2.1 High drain current capability………………………74
5.2.2 Control of the threshold voltage……………………77
5.2.3 High intrinsic transconductance………………………78
Chapter 5 References……………………………………………81
Chapter 6 Conclusions………………………………………………82
dc.language.isoen
dc.subject射頻磁控濺鍍zh_TW
dc.subject薄膜電晶體zh_TW
dc.subject氧化鋅zh_TW
dc.subject氧化鋅鎵zh_TW
dc.subject二維電子雲zh_TW
dc.subjectThin-film transistoren
dc.subject2DEGen
dc.subjectGZOen
dc.subjectzinc oxideen
dc.subjectsputteringen
dc.title利用二維電子雲效應製作氧化鋅�氧化鋅鎵多重通道薄膜電晶體zh_TW
dc.titleZnO/GZO Multi-channel Layer Thin Film Transistors Using the Effect of 2DEGen
dc.typeThesis
dc.date.schoolyear97-2
dc.description.degree碩士
dc.contributor.oralexamcommittee陳奕君(I-Chun Cheng),彭隆瀚(Lung-Han Peng),管傑雄(Chieh-Hsiung Kuan)
dc.subject.keyword薄膜電晶體,氧化鋅,氧化鋅鎵,二維電子雲,射頻磁控濺鍍,zh_TW
dc.subject.keywordThin-film transistor,zinc oxide,GZO,2DEG,sputtering,en
dc.relation.page83
dc.rights.note有償授權
dc.date.accepted2009-07-31
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept光電工程學研究所zh_TW
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