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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 顧孟愷(Mong-Kai Ku) | |
dc.contributor.author | Chao-Yuan Yu | en |
dc.contributor.author | 游超元 | zh_TW |
dc.date.accessioned | 2021-06-15T02:46:05Z | - |
dc.date.available | 2014-08-18 | |
dc.date.copyright | 2009-08-18 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-08 | |
dc.identifier.citation | [1] Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite applications, ETSI Std. EN 302 307 v1.1.1 2005.
[2] R. Gallager, 'Low-Density Parity-Check Codes,' IRE Trans. Inf. Theory, vol.7, pp. 21-28, Jan. 1962. [3] D. J. C. MacKay and R. M. Neal, 'Near Shannon limit performance of low density parity check codes,' Electron. Lett., vol. 32, p. 1645, 1996. [4] D.J.C MacKay and R.M. Neal, 'Good code based on very sparse matrices,' in Cryptography and Coding, 5th IMA Conference. Lecture Note in Computer Science. vol. 1025, C.Boyd, Ed. Berlin, Germany: Springer,1995,pp.10-111. [5] R. Tanner, D. Sridhara, and T. Fuja, A class of group-structured LDPC codes,' Proc. of ICSTA, 2001 [6] IEEE P802.11nTM/D2.00, 'Draft STANDARD for information technology, telecommunications and information exchange between systems, local and metropolitan area networks, specific requirements- Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Enhancements for Higher Throughput,' IEEE 802.11 document, Feb. 2007. [7] IEEE Std 802.16e-2005 and IEEE Std 802.16-2004/Cor 1-2005, 'IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems,' IEEE 802.16e document, Feb. 2006. [8] Y. Kou, S. Lin, and M. Fossorier, 'Low-density parity-check codes based on finite geometries: arediscovery and new results,' Information Theory, IEEE Transactions on, vol. 47, no. 7, pp. 27112736, 2001. [9] T.J. Richardson and R.L. Urbanke, 'Efficient encoding of low-density parity-check codes,' IEEE Trans. Inform. Theory, vol.47, no.2 pp. 638- 656, Feb. 2001. [10] T.J. Richardson and R.L. Urbanke, 'Modern Coding Theory,' Cambridge, Mar, 2008. [11] C. Yoon, E. Choi, M. Cheong, and S.-K. Lee, 'Arbitrary bit generation and correction technique for encoding QC-LDPC codes with dual-diagonal parity structure,' IEEE Wireless Communications and Networking Conference, (WCNC 2007), pp. 662-666, March 2007. [12] D. U. Lee, W. Luk, C. Wang, C. Jones, M. Smith and J. Villasenor, 'A Flexible Hardware Encoder for Low-Density Parity-Check Codes,' Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 101 - 111, April 2004. [13] S. Kopparthi and Don. M. Gruenbacher, 'A high speed exible encoder for low density parity check codes,' 49th IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006. [14] Z. Khan, T. Arslan and S. Macdougall, 'A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor,' IEEE International SOC Conference, pp. 17-20, Sept. 2006. [15] Y. Sun, M. Karkooti and J. R. Cavallaro, High Throughput, Parallel, Scal- able LDPC Encoder/Decoder Architecture for OFDM Systems,' IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, pp. 39-42, Oct. 2006. [16] C. Yoon, J.-E. Oh, M. Cheong, and S.-K. Lee, A hardware efficient LDPC encoding scheme for exploiting decoder structure and resources,'IEEE Vehicular Technology Conference (VTC2007-Spring), pp. 2445-2449, April 2007 [17] Z. Cai, J. Hao, P.H. Tan, S. Sun, and P.S. Chin, 'E_cient encoding of IEEE 802.11n LDPC codes,' Electronics Letters, vol. 42, no. 25, pp. 1471-1472, Dec. 2006. [18] Perez, J.M. Fernandez, V. , 'Low-cost encoding of IEEE 802.11n,' Electronics Letters, vol.44, issue 4, Feb 2006. [19] http://www.xilinx.com/products/silconsolutions/fpgas/virtex/virtex4/index.htm [20] http://www.xilinx.com/products/design resources/proc central/microblaze.htm [21] http://www.model.com/products/products se.asp [22] S. Kopparthi and D. M. Gruenbacher, 'Implementation of a flexible encoder for structured low-density parity-check codes,' IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim 2007), pp.438-441, Aug. 2007. [23] C.-Y. Lin, C.-C. Wei, and M.-K. Ku, 'Efficient Encoding for Dual-Diagonal Structured LDPC Code Based on Parity bits Prediction and Correction,' IEEE Asia Pacific Conference on Circuits and Systems (APPCCAS), pp.1648-1651, Dec. 2008 [24] Jeong Ki KIM1, Hyunseuk YOO1 and Moon Ho LEE1, 'Efficient Encoding Architecture for IEEE 802.16e LDPC Codes, ' IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44229 | - |
dc.description.abstract | 在這篇論文我們實做了一個IEEE 802.16e 編碼器在FPGA上,我們利用同位元預測與修正的方式來降低在編碼過程中的資料相依性。這個編碼器可以運用在802.16e標準裡的所有碼率和碼長。此篇論文架構能有效的降低硬體複雜度和硬體面積大小並動態的在碼率1/2, 2/3, 3/4, 5/6 和碼長 576 到 2304之間切換. 其結果顯示我們所提出的編碼器架構,無論在生產率和每面積單位生產率上,都勝過一般的的編碼器。 | zh_TW |
dc.description.abstract | In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T02:46:05Z (GMT). No. of bitstreams: 1 ntu-98-R95922162-1.pdf: 2319619 bytes, checksum: bc7b6edf253ef37a4e6b433daa73e8c0 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 口試委員會審定書 i
摘要 ii ABSTRACT iii CONTENTS iv Chapter 1 Introduction 1 1.1 The Error Correction Codes 1 1.2 Low-Density Parity-Check Codes 3 1.3 Structured LDPC Codes 4 1.3.1 Quasi-Cyclic (QC) LDPC codes 5 1.4 LDPC Codes for IEEE Standards 6 1.4.1 QC-LDPC Codes With Dual-Diagonal Structure 6 1.4.2 Code description 1 1.5 Thesis Organization 2 Chapter 2 Related work 3 2.1 General Encoding Algorithm for LDPC Codes 3 2.1.1 RU Algorithm 4 2.1.2 Encoding Complexity 8 2.2 Efficient Encoding for Dual-Diagonal LDPC Codes 8 2.2.1 Characteristics of inverse matrix of T 8 2.2.2 Linear Encoding 10 2.3 Arbitrary Bit-generation and Correction Encoding 11 2.3.1 Encoding Concept 11 2.3.2 Encoding Scheme 12 2.3.3 Summary 13 Chapter 3 Encoder architecture design 14 3.1 Encoder scheme 14 3.1.1 Algorithm 14 3.1.2 Advantage of the algorithm used 17 3.2 Encoder architecture 17 3.2.1 Parallel Architecture 18 3.2.2 Serial Architecture 23 3.3 Summary 26 Chapter 4 Implement result 28 4.1 Hardware Development Environments 28 4.2 FPGA design flow 29 4.2.1 C module and simulation 29 4.2.2 RTL Code Coding 30 4.2.3 RTL Simulation 30 4.2.4 FPGA Implementation 30 4.3 Implementation result 31 4.4 Compare to related work 36 Chapter 5 Conclusion and future work 42 5.1 Conclusion 42 5.2 Future work 42 Reference 43 | |
dc.language.iso | en | |
dc.title | 高效率IEEE802.16e編碼器設計與實作 | zh_TW |
dc.title | An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 洪士灝(Shih-Hao Hung),林宗男(Tsung-Nan Lin),廖俊睿(Jan-Ray Liao) | |
dc.subject.keyword | 低密度奇偶校驗碼,802.16e, | zh_TW |
dc.subject.keyword | LDPC,802.16e, | en |
dc.relation.page | 45 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-08-10 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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