半導體製程中對於疊對控制所需取樣計畫最佳化

Abstract

現今半導體元件係為立體結構，其係由一層一層的平面結構逐漸堆疊而來。是故兩層之間的相對位置需要有很高的精確性。以確定元件能正常運作，避免像短路之類的問題發生。這些都會影響到積體電路的良率及效能。近年來隨著微影技術的進步，元件尺寸得以縮減，而對準的需求也隨之提昇。為了滿足現今疊對需求，高階模型及個域對準皆需被導入來克服目前的問題。為此需要大量的疊對量測資料。然而在其中，不同的取樣方式可能導致一些疊對修正上的問題。為判斷目前取樣方式的合適性，最大疊對預測誤差可以做為判斷依據。首先我們為了符合能同時達到低耗時，高疊對精準性的經濟考量，做了疊對中各項變因所佔組成的研究。接著我們分析了以各取樣點的資料為主時所獲得的最大疊對預測誤差。這個步驟將能協助我們找尋最適取樣以完成疊對參數的估測。最後我們將以模擬結果來證明我們提出的方法可行。

A modern semiconductor device exists in three dimensions: throughout the course of its manufacturing, a chip experiences the patterning of approximately two dozen different layers, each of which must be precisely positioned with respect to the one beneath. In order to ensure the correct operation of the final device, this positioning (or alignment) is necessary to avoid the following problems like contact shorting to gate, and contact impinging on isolation. That will affect directly IC yield and performances. Over the years that lithography has been evolving, overlay alignment requirements have generally scaled linearity with the minimum feature size. For matching current overlay requirement, high order overlay model and field-to-field alignment have been applied to overcome this challenge. For applying these strategies more overlay measurement needs to be considered. However different overlay sample plans could led different results. The MOPE - maximum overlay predicted error could be used for judge current sample plan is suitable or not. First we analyse each component of overlay error to decide which model of order will match our economical requirement in both time consumption and overlay residual. Then we will proceed to analyse the MOPE based on single overlay data of each referred target which is partially chosen from original overlay data. This procedure will help us to find suitable samples for overlay parameter evaluation. Eventually, we will simulate our proposed control method using the Matlab software for the demonstration.