請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43594完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張時中(Shi-Chung Chang) | |
| dc.contributor.author | Rong-Huei Chen | en |
| dc.contributor.author | 陳榮輝 | zh_TW |
| dc.date.accessioned | 2021-06-15T02:24:02Z | - |
| dc.date.available | 2009-08-21 | |
| dc.date.copyright | 2009-08-21 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-18 | |
| dc.identifier.citation | Bibliography
[1] S.-J. Hsu, C.-M. Fan, W.-C. Lin, S.-C. Chiou, “A Methodology for On-Demand Engineering Service with Resource Integration and Reuse at Knowledge Level,” Proceedings of the 12th Annual International Conference on Industrial Engineering Theory, Applications and Practice, Cancun, Mexico, Nov. 4-7, 2007, pp635-643. [2] J.-R. Lee, S.-C. Chang, F.-H. Su, C.-M. Fan, “Service Oriented Platform Design for Collaborative Engineering Data Analysis,” Proceedings of 2007 International Symposium on Semiconductor Manufacturing, San Jose, California, Sept. 25-27, 2007, pp. 245-248. [3] W.-C. Lin, “Modeling of Yield Analysis Procedure (YAP) Knowledge at Engineering Purpose Level,” Master Thesis, Industrial Engineering Department, National Taiwan University, Taipei, Taiwan, June 2008. [4] J. Lee, H. Suh and S.-H. Han, “Ontology-based knowledge framework for product development,” Computer-Aided Design and Applications, Vol 2, No. 5, 2005, pp. 635-643. [5] S.-J. Hsu, “Design of an Enabling Mechanism for Effective Yield Analysis Procedure,” Master Thesis, Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, June 2007. [6] F.-H. Su, “Knowledge Engineering for Semiconductor Yield Analysis: Tool Application and Fault Symptom Identification,” Master Thesis, Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, June 2008. [7] J.-F. Sowa, Semantic networks,” in S.C. Shapiro (ed.), Encyclopedia of Artificial Intelligence, New York, 1992, pp.1493-1511. [8] C.-F. Chien, W.-C. Wang, J.-C. Cheng, “Data mining for yield enhancement in semiconductor manufacturing and an empirical study,” Expert Systems with Applications, vol. 33, issue 1, July 2007, pp.192-198. [9] M. Sugimoto and H. Hamada, “Yield Enhancement Using a Memory Expert System Linked to the Wafer Inspection Tool,” Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995, Nov. 13-15, 1995, pp. 282- 286. [10] S. Peters and Shrobe, “Using semantic networks for knowledge representation in an intelligent environment,” IEEE International Conference on Pervasive Computing and Communications, H.E. 2003, pp.323-329. [11] S.-F. Lau and F.-L. Chen, “A Data Clustering Model for Wafer Yield Loss in Semiconductor Manufacturing,” Journal of the Chinese Institute of Industrial Engineers, vol. 21, No. 4, pp. 328-338, 2004. [12] Genesereth and M.-R. Nilsson, “Logic foundations of artificial intelligence,” San Francisco: Morgan Kaufmann Publishers, N.J. 1987 [13] S. Staab, and R. Studer , Handbook on Ontologies, Springer, 2004 [14] W. M. P. V. Aalst and B. F. V. Dongen. “Workflow mining: A survey of issues and approaches,” Data and Knowledge Engineering, vol. 47, issue 2, Nov., 2003, pp. 237-267 [15] S.-F. Liu, F.-L. Chen and W.-B. Lu, 'Wafer Bin Map Recognition Using a Neural Network Approach,' International Journal of Production Research, Vol.40, No.10, 2002, pp.2207-2224, [16] S.-C. Chang, Y.-T. Lin, Y.-J. Chang, S.-K. Jeng, B.-W. Hsieh, “Learning Software Agent Design for Semiconductor Tool Group Dispatching,” Proceedings of 2004 Semiconductor Manufacturing Technology Workshop, Sept. 9-10, 2004, pp.21-24 [17] C.-M. Fan, S.-C. Chang, H. Chang, “Design of Collaborative Engineering Data System (CEDS): an Application Case of Process Integration,” Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on, San Jose, CA, Sept. 2005, pp. 43-46 [18] N.-F. Noy and D.-L. McGuinnessl, “Ontology Development 101: A Guide to Creating Your first Ontology,” Technological report, Stanford University, Stanford, CA, 2001, pp.2 [19] T.-R. Gruber, “A translation approach to portable ontology specifications,” Knowledge Acquisition, vol. 5, no. 2, 1993, pp. 199-220 [20] S. Russell, P. Norvig, Artificial Intelligence: A Modern Approach, 2/E, Prentice Hall, 1995, pp.211 [21] M.-H Gruninger,., and R. Mcllraith, “FLOW: A First-Order Ontology for Semantic Web Services,” W3C Workshop on Frameworks for Semantics in Web Services, S. A. 2005 [22] IBM, Service Oriented Architecture-SOA: http://www-306.ibm.com/software/ solutions/soa/ [23] J.-M. Pork, J.-H. Nam, Q.-P. Hu, “Product Ontology Construction from Engineering Document,” International Conference on Smart Manufacturing Application, April, 2008, pp305-309. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43594 | - |
| dc.description.abstract | 在工程鏈管理中，快速的良率提升(Yield enhancement)是ㄧ關鍵性的面向。在次波長的晶圓製造時代，高額的投資、市場需求的快速變遷，加上日益複雜的晶圓製造流程，機台與操作，使得半導體廠對於晶圓製造的週期時間需求也是越加的迫切。快速的良率提升是基於有效的良率分析(Yield analysis)知識管理。
在半導體製造中，在晶圓的電性偏移下，工程師常會藉著監控晶圓允收參數(WAT)去診斷問題的根源。在良率分析中，為了儲存與利用晶圓允收參數(WAT)，工程師會對晶圓允收參數命名。除了依據命名的基本方針(guideline)外，工程師也常使用個人的命名規則去對晶圓允收參數命名，而他人未必知道。因此會產生兩種名字無法對齊的情況:一個名字可能代表兩個不同的晶圓允收參數，或是一個相同的晶圓允收參數可能會有數個名字。本論文研究以既存的晶圓允收測試參數名稱的對齊作為我們研究的載具問題，來設計機制，可以自動的對齊既有的名字(legacy name)，並建立統一命名 (golden name)的基礎，以達到知識的分享與重複使用，進而提高良率分析的效率。 機制設計的挑戰如下: 1)如何自動萃取晶圓允收測試資料命名知識與建模? 2)如何在不需要額外的時間下，自動的對齊現有的元件測試參數舊有的名字與統一的名字? 針對兩項挑戰所設計的機制如下: 1. 晶圓允收測試資料命名知識(WATDINK)模型的建置：以本體論(ontology)為基礎的晶圓允收測試資料命名知識描述。我們首先採用一階邏輯(FOL)建模因為它有良好的邏輯解釋能力,然後我們將一階邏輯轉換成語意網路（semantic network）建模，使工程師更容易理解。語意網路（semantic network）包含節點類型（node type）、節點（node）與節點聯結（node link）。在晶圓允收測試資料命名知識中，節點對應到資料名稱如晶圓允收測試項目(WAT measure item)，而節點類型為具有相同性質的點的集合，包含「元件概念」、「晶圓允收參數概念」、「測試線概念」與「測試方法概念」，節點聯結則是對應到兩個節點之間的關係（relation），包含「繼承」、「測量」、「輸入」與「輸出」。藉由這個晶圓允收測試資料命名知識模型，來萃取晶圓允收測試資料命名知識。 2. 自動的對齊既有的名字: 本設計由兩個以晶圓允收測試資料命名知識模型為基礎的演算法所構成: 名字描述(WATDIND )演算法與對齊(WATDINNA)演算法。名字描述(WATDIND )演算法藉由晶圓允收測試資料命名知識(WATDINK)模型中的節點聯結，從現有的元件測試資料的名稱中萃取出節點值(node value), 然後記錄在晶圓允收測試資料名字描述表。對齊(WATDINNA)演算法先分別對兩筆參數名字建立本體論知識模型下的描述，再比較兩者是否相同，若是，即可對齊。若名字相同，但本體論知識模型下的描述不同，則為不同的參數。 為了展現我們設計的機制的可行性，將所設計的機制設計成一個模組(module)，並整合在一個服務導向架構(Service Oriented Architecture, SOA)為基礎概念性工程資料分析平台上，獲致如下的功效: 1. 藉由以本體論為基礎的晶圓允收測試資料命名知識模型(WATDINM)的建立，可以從已經存在的檔案中萃取晶圓允收測試資料命名知識。 2. 藉由將原本兩兩對照的比對方法改變成以本體論為基礎的比對方法，可以使容易顯著的減少建造命名對照表所需的負擔。 3. 可以自動而且準確的對齊既有的名字，幫助工程師更容易利用其他分析工具分析晶圓允收測試資料並作為建立統一命名方法的基礎。 | zh_TW |
| dc.description.abstract | Quick yield enhancement is one of the critical aspects of engineering chain management. In the sub-wavelength era, cycle time requirement becomes more stringent because capital investment is sky rocketing while market demands change more rapidly and the manufacturing process, equipments and operations become more complicated than before. Fast yield ramping is founded on effective management of knowledge intensive yield analysis.
In semiconductor manufacturing, wafer-acceptance-test (WAT) data is monitored to detect if there are electrical performance deviations and then to diagnose the root causes of manufacturing processes. To store and retrieve WAT data for yield analysis, engineers perform WAT data naming, engineers have individual naming rules under the guideline to do WAT naming and the naming rule knowledge is often kept to individual engineers. As a result, two types of misalignment of WAT data naming may occur: one same WAT data item with different names or a WAT data item name representing several WAT data items. In this thesis, we investigate legacy WAT naming alignment problem and focus on design of automatic WAT naming alignment among legacy WAT data names to facilitate effective sharing and reuse in yield analysis. Specific design challenges are as follows: C1) How to extract and represent knowledge of WAT data item naming and C2) How to automatically align WAT legacy names to golden names without requiring extra effort Two mechanisms are designed to conquer these challenges respectively as follow: 1. Establishment of ontology-based WAT data item naming knowledge model (WATDIKM): Ontology-based knowledge representation mechanism, we adopt first order logic (FOL) approach because of good logical expression, and transfer FOL into semantic network (SN) modeling approach for the purpose of easier comprehension by engineer. Semantic network consist of node types, nodes and node links. In the context of WAT data item naming, nodes correspond to concepts like WAT measure item, etc, while the nodes which have the same property are classified into a node type which include “Device Concept”, “WAT Concept”, “Test Line Concept” and “Test Method Concept.” Node link corresponds to the relation between two nodes. Node link contain “Inherit”, “Measure”, “Input” and “Output.” The knowledge of WAT data item naming are represented by WAT data item naming knowledge model (WATDIKM). 2. Establishment of automation alignment mechanism: This mechanism includes WAT data item name description algorithm (WATDIND) and WAT data item naming alignment algorithm (WATDINA). WATDIND algorithm can extract node value of WAT data item from existing WAT data naming by node links of WATDNKM. And node values are stored in ontological WAT data item name description table. Based-on WATDNKM, WATDINNA algorithm constructs WAT data item name descriptions for the two data names. Afterward, compare the two data name description. If data name descriptions are the same, then they can be aligned. If the two WAT data items have the same name and different name descriptions, they are not the same data item. To reveal the knowledge extraction mechanisms which are achievable, the three new designs have been implemented as module and integrated into a Service Oriented Architecture (SOA) based EDA platform. The three main values of the platform are enhanced by the mechanisms as follow: 1. Knowledge of WAT data item naming can be extracted from existing data by constructing the ontology–based WAT data item naming knowledge model (WATDINKM). 2. facilitates significant reducing in name mapping table constructing effort by change pair-wise alignment method to ontology-based alignment method 3. Provide fast and accurate WAT naming alignment to facilitate quick analysis WAT data by analysis tools and foundation of establishing golden names. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T02:24:02Z (GMT). No. of bitstreams: 1 ntu-98-R96921003-1.pdf: 4487425 bytes, checksum: 532a87d169d95eef44bc36123147aad0 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Contents
摘要 1 Abstract 3 Contents 7 List of Figures 9 List of Tables 11 Chapter 1 Introduction 13 1.1 Challenges and Significance of WAT Naming Alignment 14 1.2 Literature Survey 15 1.3 Scope of Research 16 1.4 Thesis Organization 18 Chapter 2 Wafer-Acceptance Test Naming Alignment Problem Formulation 21 2.1Wafer-Acceptance-Tset Parameter Naming 22 2.1.1 Wafer-Acceptance-Test Data 22 2.1.2 Naming Practice of Wafer-Acceptance-Test 25 2.1.3 Current WAT Naming Alignment 29 2.2 Problems Formulation of WAT Legacy Naming Alignment 31 2.3 Challenges of WAT Naming Alignment 35 Chapter 3 Ontology-based WAT Data Item Naming Knowledge Model (WATDINM) Design 37 3.1 Knowledge Representation & WAT Naming Alignment 38 3.1.1 Ontology 38 3.1.2 First Order Logic 39 3.1.3 Semantic Networks 40 3.1.4 WAT Naming and Alignment as Ontology Problems 40 3.2 Introduction to FOL and SN Modeling 43 3.2.1 First Order Logic Formalism 43 3.2.2 Semantic Network Formalism 46 3.2.3 Transformation of FOL to SN 50 3.3 Design of Semantic Network Model of WAT Data Item Names Knowledge 51 3.3.1 WAT Names and WAT Testing Method Analysis 52 3.3.2 Wafer-Acceptance-Test Data Item naming knowledge Model (WATDINKM) Design 58 Chapter 4 Design of Ontology Model-based Naming and Alignment Methods 65 4.1 WAT Parameter Data Item Name Description Algorithm (WATDIND) Design 66 4.1.1 WATDIND Algorithm 66 4.1.2 WAT Legacy Names Description 72 4.1.3 WAT Golden Names Description 75 4.2 WAT Data Item Naming Alignment Algorithm (WATDINA) Design 76 4.2.1 WATPNA Algorithm 76 4.2.2 Legacy to Golden Alignment 78 4.3 Summary 82 Chap 5 Implement of WAT Parameter Naming Alignment Module 85 5.1 Proof-of-Concept Implementation 85 5.2 Potential Applications 86 5.3 Summary 93 Chapter 6 Conclusion and Future Work 95 Bibliography 99 | |
| dc.language.iso | en | |
| dc.subject | 本體論 | zh_TW |
| dc.subject | 晶圓允收參數 | zh_TW |
| dc.subject | 語意網路 | zh_TW |
| dc.subject | 命名對齊 | zh_TW |
| dc.subject | Naming Alignment | en |
| dc.subject | Semantic Network | en |
| dc.subject | Wafer-Acceptance-Test | en |
| dc.subject | Ontology | en |
| dc.title | 半導體中晶圓允收測試資料之命名對齊機制設計 | zh_TW |
| dc.title | Naming Alignment Design for Semiconductor Wafer-Acceptance-Test Data | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 范治民(Jhih-Ming Fan),蔡雅蓉(Ya-Jung Tsai),高慶斌(Ching-Pin Kao),陳正剛(Argon Chen) | |
| dc.subject.keyword | 本體論,晶圓允收參數,語意網路,命名對齊, | zh_TW |
| dc.subject.keyword | Ontology,Wafer-Acceptance-Test,Semantic Network,Naming Alignment, | en |
| dc.relation.page | 101 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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