使用0.5V多重臨界電壓技術單相位時序(TSPC)動態邏輯電路於乘法器設計

Abstract

本篇論文研究主要是探討動態電路使用BP-DTMOS/MTCMOS技術於全加器以及乘法器在功率消耗與速度的最佳化。 首先敘述CMOS技術的發展趨勢以及超大型積體電路低電壓操作的需求，並且介紹BP-DTMOS技術。第二章描述低電壓下使用BP-DTMOS/MTCMOS具有閂鎖(TSPC)以及沒有閂鎖(NORA)動態電路的操作原理，除此之外使用BP-DTMOS/MTCMOS技術的全加器電路也被敘述。第三章敘述一個動態邏輯電路以及BP-DTMOS/MTCMOS技術的（pipeline）TSPC乘法器電路。第四章則是結論與未來研究方向。

This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are described. Then BP-DTMOS technology is introduced. Chapter 2 describes the principle of low voltage dynamic logic circuit with and without latch using BP-DTMOS/MTCMOS technology. In addition， a full adder circuit using BP-DTMOS/MTCMOS technology is described. In Chapter 3， a dynamic logic circuit and DTMOS/MTCMOS technology pipelined multiplier using the 0.5V true single-phase clock (TSPC) is described. Chapter 4 is the conclusion and future work of this research.