可變區塊大小之移動估測演算法與硬體架構

Abstract

在嵌入式系統中，多媒體已變得越來越重要。誠如大家所知，移動估測在視訊壓縮中 扮演重要的角色，由於兩張連續的影像通常差異並不大，尤其在較高的畫面更新率下 差異更小，所以移動估測藉由利用視訊資料中時間冗餘資訊來達成視訊壓縮。 最新的編碼標準H.264採用了相當多新的技術。例如為了要能夠在畫面中選擇更合 適的區塊，H.264採用了可變區塊大小之移動估測，相較於先前的技術，編碼效能大幅 地提升。然而，H.264的計算複雜度也大幅地增加。在編碼器中的所有技術之中，移動 估測正是最花時間的功能。尤其是使用軟體的方法來實現。 本文針對可變區塊大小之移動估測結合了軟體和硬體的最佳化。在軟體最佳化方 面，我們提出了一個新的演算法，將移動向量分群，以便能夠更有效率的選擇合適的 區塊。在硬體方面，我們使用了平行化管線的技術來提升效能。我們使用了現場可程 式化邏輯陣列來實現這個架構。整個電路可以操作在311Mhz，而僅用掉65k的閘。結 果顯示我們的架構在248Mhz之下可以達到每秒30張1920x1080解析度的16x16全域搜 尋移動估測。就單位面積的產量來看，我們提出的架構可以達到更高的硬體效率。

Multimedia has become more and more important in embedded systems. It is well-known that the motion estimation plays an essential role in video coding. It is also the key elements that achieve video compression by exploiting temporal redundancy of video data because the di erence between two successive frames are usually very small, especially for high frame rates. The latest coding standard H.264 has adopted lots of new features. For in- stance, in order to adaptively choose the proper block size for frame macroblock, H.264 has used variable block size motion estimation which can signi cantly im- prove the coding performance compared to previous techniques. However, the computational complexity of H.264 has also increased drastically. Among all the techniques in the encoder, motion estimation is exactly the most time-consuming function especially when it is implemented in a software approach. In this thesis, we combine software and hardware optimizations for variable block size motion estimation. At the software level, we propose a new algorithm that can e ciently select a suitable block size by grouping the motion vectors. At the hardware level, we propose a pipelined and parallel architecture to enhance the performance. Our architecture is implemented on an FPGA platform. It operates at a maximum clock frequency of 311 MHz with gate count 65k. The results show that under a frequency of 248MHz, our architecture allows the pro- cessing of 1920x1080 at 30fps with full search motion estimation in a 16x16 search range. This proposed architecture provides a better hardware e ciency in terms of throughput and gate count than previous works.