Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42756Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Chia-Jui Lee | en |
| dc.contributor.author | 李佳叡 | zh_TW |
| dc.date.accessioned | 2021-06-15T01:22:08Z | - |
| dc.date.available | 2010-06-30 | |
| dc.date.copyright | 2010-06-30 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-23 | |
| dc.identifier.citation | References
[1] W. Shottkley, “Semiconductor translating device,” U.S. Patent 266814, filed 1949. [2] D.Kahng and M.M. Atalla, “Silicon-Silicon Dioxide Surface Device,” IRE Device Research Conference, Pittsburgh, 1960. [3] G. E. Moore, “Progress in digital integrated circuit,” IEDM tech. Dig., p.11, 1975. [4] International Technology Roadmap for Semiconductors (ITRS), 2008 Edition. [5] D.A. Buchanan, IBM J. Res. Dev., Vol. 43, pp. 245, 1999 [6] Y. Y. Fan, R. E. Nieh, J. C. Lee, G. Lucovsky, G. A. Brown, L. F. Register, and S. K. Banerjee, “Voltage- and temperature-dependent gate capacitance and current model: application to ZrO2 n-channel MOS capacitor,” IEEE Trans. Electron Devices,Vol. 49, pp. 1969-1978, 2002. [7] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide/silicon structure,” IEEE Electron Device Lett., Vol. 23,pp. 97-99, 2002. [8] E. H. Nicollian and J. R. Brews, “Interface traps: bond models” MOS Physics and Technology, pp.823, 1981. [9] P. M. Lenahan, J. J. Mele, J. P. Campbell, A. Y. Kang, R. K. Lowry, D. Woodbury, S. T. Liu and R. Weimer, “Direct experimental evidence linking silicon dangling bond defects to oxide leakage currents” IEEE International, Reliability Physics Symposium, pp. 150-155, 2001. [10] J. Y. Yen, C. H. Huang, and J. G. Hwu, “Effect of Mechanical Stress on the Characteristics of Silicon Thermal Oxides”, Japanese Journal of Applied Physics, Vol.41, Part 1, No.1, pp.81-82, 2002. [11] Y. C. Chen “Ultra-thin gate Oxide prepared by the application of alternative current anodization of silicon,” Master’s dissertation, Dept. Elect. Eng., Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2000. [12] A. Nara, N. Yasuda, H. Satake, and A. Toriumi, “Applicability Limits of the Two-frequency Capacitance Measurement Technique for the Thickness Extraction of Ultrathin Gate Oxide,” IEEE Trans. on Semicon. Manufacturing, Vol. 15, pp. 209-213, 2002. [13] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. F. Wang, L. G. Yao, S. C. Chen, C. H. Yu, and M. S. Liang, “Determination of Deep Ultrathin Equivalent Oxide Thickness (EOT) From Measuring Flat-Band C–V Curve,” IEEE Transactions on Electron Devices, Vol. 49, pp. 695-698, 2002. [14] K. J. Yang and C. Hu, “MOS capacitance measurements for high-leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 1500–1501, 1999. [15] K. Yang, Y. C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Proc. Symp. VLSI Tech., pp. 77–78, 1999. [16] Berkeley Device Group. [Online]. Available: http://www-device.eecs.berkeley.edu/index.htm. [17] G. C. Jain, A. Prasad and B. C. Chakravarty, “On the mechanism of the anodic oxidation of Si at constant voltage,” J. Electrochem. Soc., Vol. 126, pp. 89-92, 1979. [18] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical properties of SiO2 thin films obtained by anodic oxidation,” Journal of Molecular Structure, pp. 607-610, 1999. [19] C. C. Ting, Y. H. Shih, and J. G. Hwu, “Ultra Low Leakage Characteristics of Ultra-thin Gate Oxides (~3 nm) Prepared by Anodization Followed by High Temperature Annealing”, IEEE Transactions on Electron Devices, Vol.49, pp.179-181, 2002. [20] C. C. Ting and J. G. Hwu, “Low Leakage and High Breakdown Endurance Ultra-thin Gate Oxides Prepared by Anodization Technique,” Master Thesis, Dept. of Electrical Engineering, N.T.U. 2000. [21] T. H. Lee and J. G. Hwu, “Investigation of Ultra-thin Gate Oxides Prepared by Anodization with Tensile Stress in Tilted Cathode Anodization System,” Master Thesis, GIEE, N.T.U. 2006. [22] Y. H. Shih, S. R. Lin, T. M. Wang, and J. G. Hwu, “High Sensitive and Wide Detecting Range MOS Tunneling Temperature Sensors for On-Chip Temperature Detection”, IEEE Transactions on Electron Devices, Vol.51, pp.1514-1521, 2004. [23] Y. P. Lin and J. G. Hwu, 2004, “Oxide Thickness Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” Journal of The Electrochemical Society, Vol.151, No.12, G853-G857. [24] Ashcroft and Mermin, Solid state physics, pp. 32–38(Harcourt, 1975). [25] Chih–Hung Tseng, “Germanium Channel MOSFETs and Strain–Induced Effects on Silicon MOS Capacitor”, p69. [26] C.C.Wang, T.H.Li, K.C.Chuang and J.G.Hwu*, “Ultra-thin Gate Oxides Prepared by Tensile-Stress Oxidation in Tilted Cathode Anodization System,” Journal of the Electrochemical Society, 155 (s), G61-G64, 2008. [27] N. W. Ashcroft and N. D. Mermin, Solid State Physics, pp. 32-38, Holt,Rinehard, and Winston, New York, 1976. [28] C. H. Tseng, “Germanium Channel MOSFETs and Strain-Induced Effects on Silicon MOS Capacitor”, p69. [29] Degraeve, R., et al., “A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides” in IEDM, p.863, 1995. [30] Harari, E., “Dielectric breakdown in electrical stressed thin films of thermal SiO2” J. Appl. Phys., 1978. 49(4): p.2478. [31] Rico, B., M. Y. Azbel, and M.H. Brodsky, “Novel Mechanism for Tunneling and Breakdown of Thin SiO2 Films,” Phys. Rev. Lett., 1983. 51(19): 1795. [32] C. C. Wang and J. G. Hwu, “High Quality Ultra-thin Gate Oxides Prepared by Tensile-Stress Anodization Technique,” Master Thesis, GIEE, N.T.U. 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42756 | - |
| dc.description.abstract | 在先進的半導體製程技術，金氧半元件縮小至深次微米區域，矽氧化層的厚度也隨之縮小。根據國際半導體技術藍圖（ITRS）的預測，西元2012年時，元件的等效氧化層厚度將會是0.75奈米，此時的矽氧化層因為太薄而導致大量漏電流，因而有高介電質材料作為金氧半元件絕緣層的考慮。然而，由於高介電質材料的不穩定等問題，矽氧化層仍是非常重要的課題。在本篇論文中，我們採用另一種直接成長二氧化矽於基板上的方法－陽極氧化。陽極氧化的優點在於超薄閘極氧化層的厚度控制及可在室溫下成長氧化層的特點。在成長氧化層的過程當中，我們藉著機械應力彎曲矽晶圓的方式及交直流增進金氧半元件氧化層的品質。元件的電特性及穩度度分析在利用傾斜陰極之陽極氧化系統生長不同厚度之氧化層將會被仔細地探討。實驗結果證明，無論是機械張力或是交直流電技術成長氧化層，都能增進元件的電特性及穩定度。最後，我們對這篇論文給予結論及建議未來的研究方向。 | zh_TW |
| dc.description.abstract | In advanced technology of semiconductor, MOS devices are scaled down to deep-submicrometer region. As a result, thickness of silicon oxide also scales down. Based on the International Technology Roadmap for Semiconductor (ITRS), the equivalent oxide thickness (EOT) should be scaled to 0.75 nm in 2012. It is too leaky for ultra-thin gate silicon oxide so high-k films are introduced to solve the problem. However, silicon dioxide is still of interest due to the existing problems in high-k gate dielectrics. In the thesis, we introduce an alternative way to directly grow SiO2 on silicon substrate, i.e., anodization. The advantage of anodization includes good control of the thickness of ultra-thin gate oxides as well as the process can be held at room temperature. In addition, we improve the quality of oxide by applying mechanical tensile stress on silicon wafer and giving direct current superimposed with alternating-current (DAC) during anodization. The electrical characteristics and reliability of different oxide thickness prepared by tilted cathode anodization system will be discussed. From the experimental results, we demonstrate the quality of gate oxides would be improved in electrical characteristics and reliability test by either tensile-stress or DAC. Finally, conclusions and some other suggestions for future work about this thesis were given. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T01:22:08Z (GMT). No. of bitstreams: 1 ntu-98-R96943063-1.pdf: 1209996 bytes, checksum: fa04d8c5355aa14278e9961942e0595b (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Content
摘要 I Abstract III Content V Figure Captions VII Chapter 1 Introduction 1 1.1 Motivation of This work 1 1.2 Experimental Setup and Measurement Tools 5 1.3 Theoretical Models of MOS Capacitors 5 1.4 Anodization and Anodized Gate Oxides 9 1.5 Summary 10 Chapter 2 Tilted Cathode Tensile-Stress and Direct-Current Superimpesed with Alternating-Current Anodizations 14 2.1 Introduction 15 2.2 Experimental 16 2.3 Device Characterization 19 2.3.1 C-V curves 19 2.3.2 J-V curves 20 2.3.3 Leakage current comparisons 21 2.3.4 Flat-band voltage shift 23 2.4 Summary 25 Chapter 3 Reliability of Oxides Prepared by Tilted Cathode Tensile-Stress Anodization and DAC-ANO Technique 40 3.1 Introduction 41 3.2 Reliability 41 3.2.1 TDDB reliability 42 3.2.2 TZDB reliability 45 3.3 Interface Traps 45 3.4 Oxide Growth Kinetics 46 3.5 Summary 48 Chapter 4 Conclusions and Future Work 61 4.1 Conclusions 61 4.2 Future Work 62 References 64 | |
| dc.language.iso | en | |
| dc.subject | 陽極氧化 | zh_TW |
| dc.subject | 金氧半電容 | zh_TW |
| dc.subject | 伸張應力氧化 | zh_TW |
| dc.subject | Metal-oxide-semiconductor (MOS) | en |
| dc.subject | Tensile-stress oxidation | en |
| dc.subject | Anodization (ANO) | en |
| dc.title | 以伸張應力及直流疊加交流之陽極氧化法成長超薄閘極氧化層 | zh_TW |
| dc.title | Ultra-thin Gate Oxides Prepared by Tensile-Stress and Direct-Current Superimposed with Alternating-Current Cathode Anodization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王維新(Way-Seen Wang),鄭晃忠(Huang-Chung Cheng),洪志旺(Jyh-Wong Hong) | |
| dc.subject.keyword | 陽極氧化,金氧半電容,伸張應力氧化, | zh_TW |
| dc.subject.keyword | Anodization (ANO),Metal-oxide-semiconductor (MOS),Tensile-stress oxidation, | en |
| dc.relation.page | 67 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-98-1.pdf Restricted Access | 1.18 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.