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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42485
標題: | 低功率連續漸進式及管線式類比數位轉換器之設計與應用 Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters |
作者: | Po-Hsiang Fang 方柏翔 |
指導教授: | 呂學士(Shey-Shi Lu) |
關鍵字: | 類比數位轉換器,連續漸進式,管線式, ADC,SAR,pipelined, |
出版年 : | 2009 |
學位: | 碩士 |
摘要: | As the rapid growth on the development of the wireless communication system, the requirement for the ADC that connect the digital and analog circuits becomes stricter and stricter. In this thesis, two kinds of ADCs are implemented that contain power-saving techniques.
In Chapter 3 of this thesis, a low power SAR ADC is presented which uses the advantage of the fully differential structure to decrease the requirement of capacitors, that makes the chip area smaller while get the same resolution as the traditional circuit. The chip is fabricated by TSMC 0.35um 2P4M CMOS technology and the measurement results will be shown. In Chapter 4, a pipelined ADC is introduced which uses opamp current reuse technique to decrease the power dissipation without summing node reset problem. As a result, we can get the advantage of pipelined ADC that has high operation speed without massive power consumption. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42485 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-98-1.pdf 目前未授權公開取用 | 7.49 MB | Adobe PDF |
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