請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42182完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 施吉昇(Chi-Sheng Shih) | |
| dc.contributor.author | Yu-Hsien Lin | en |
| dc.contributor.author | 林毓賢 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:51:18Z | - |
| dc.date.available | 2009-09-02 | |
| dc.date.copyright | 2008-09-02 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-12 | |
| dc.identifier.citation | [1] Texas Instruments, “DVEVM Getting Started Guide,” March 2007. Literature Number SPRUE66C.
[2] Texas Instruments, “Analog Technologies, Semiconductors, Digital Signal Processing-Texas Instruments.” at http://www.ti.com/. Last accessed at May 2008. [3] Texas Instruments, “Universal Multimedia Player Based on DaVinci Technology,” November 2006. Literature Number SPRT383. [4] Andrew S. Tanenbaum, Modern Operating Systems. Prentice Hall, 2nd ed., 2001. ISBN 0-13-031358-0. [5] Microsoft, “Multiprocessor Considerations for Kernel-Mode Drivers,” October 2004. [6] M. Tim Jones, “Linux and Symmetric Multiprocessing.” at http://www.ibm.com/developerworks/library/l-linux-smp/. Last accessed at May 2008. [7] Peter Koch, “History of the Sun4 Series.” at http://www.sun4zoo.de/en/history.html. Last accessed at May 2008. [8] Mathematics and Computer Science Division (MCS), “The Message Passing Interface (MPI) Standard.” at http://www-unix.mcs.anl.gov/mpi/. Last accessed at May 2008. [9] Computer Science and Mathematics Division (CSM), “PVM: Parallel Virtual Machine Webpage.” at http://www.csm.ornl.gov/pvm/. Last accessed at May 2008. [10] Sun Microsystems, “RPC: Remote Procedure Call Protocol Specification Version 2.” at http://tools.ietf.org/html/rfc1831. Last accessed at May 2008. [11] X/Open Company Limited, DCE: Remote Procedure Call. X/Open Company Ltd., U.K., 1994. ISBN 1-85912-041-5. [12] J J. Labrosse, MicroC/OS-II: The Real Time Kernel. CMP Books, 2nd ed., 2002. ISBN 1-57820-103-9. [13] A. D. Marshall, “UNIX System Calls and Subroutines using C - IPC: Shared Memory.” at http://www.cs.cf.ac.uk/Dave/C/node27.html. Last accessed at May 2008. [14] C. L. Liu and J. Layland, “Scheduling algorithms for multiprogramming in a hard real-time environment,” Journal of the ACM, vol. 20, no. 1, pp. 46-61, 1973. [15] Texas Instruments, “TMS320DM6446 Digital Media System-on-Chip,” March 2007. Literature Number SPRS238E. [16] Texas Instruments, “TMS320C64x DSP CPU and Instruction Set and Reference Guide,” July 2007. Literature Number SPRU732D. [17] ARM, “ARM926EJ-S Technical Reference Manual,” January 2004. [18] Texas Instruments, “TMS320DM644x DMSoC DSP Subsystem Reference Guide,” March 2007. Literature Number SPRUE15. [19] Open Kernel Labs, “Introduce to OKL4 of Open Kernel Labs.” at http://www.ok-labs.com/products/okl4. Last accessed at May 2008. [20] Dresden, University of Technology, “The L4 ¹-Kernel Family.” at http://os.inf.tu-dresden.de/L4/. Last accessed at May 2008. [21] Texas Instruments, “DSP/BIOS Kernel Technical Overview,” August 2001. Literature Number SPRA780. [22] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Tansactions on Circuits and Systems for Video Technology, vol. 13, July 2003. [23] Davis Pan, “A tutorial on MPEG/Audio compression,” IEEE Multimedia Journal, pp. 60-74, Summer 1995. [24] Texas Instruments, “TMS320DM644x DMSoC 64-bit Timer User’s Guide,” March 2007. Literature Number SPRUE26. [25] Xiaoli Zhao, Pin Tao, Shiqiang Yang, and Fei Kong, “Computation offloading for h.264 video encoder on mobile devices,” IMACS Multiconference on “Computational Engineering in Systems Applications”(CESA), October 4-6 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42182 | - |
| dc.description.abstract | 在多核心架構的系統中，核心間行程通訊是個重要的議題，一個效率不好的通訊
協定設計將造成系統效能下降。本篇研究針對基於異質多核心單晶片系統平台的 多媒體串流應用，提出一個有效率的核心間行程通訊協定，此協定使用三個特殊 設計的機制，達成非同步及無緩衝的通訊，並藉由移除中斷機制及減少記憶體複 製的操作來提升效能。由傳輸不同資料量的實驗可得知，所提出的協定中的'傳 送'動作只需小量的常數時間，而'接收'動作亦優於傳統行程間通訊協定，且差 距隨著資料量越大而增加；而由H.264 編碼應用的模擬結果可知，相較於傳統行 程間通訊協定，所提出的協定使得效能有大約40%的提升。 | zh_TW |
| dc.description.abstract | Inter-core communication is an important issue need to be addressed in multi-core architectures. An inefficient communication design will lead to performance degradation. In this thesis, we target on multimedia streaming application on heterogeneous multi-core SoCs and design an efficient inter-core process communication (ICPC) protocol. It is an asynchronous and un-buffer protocol which using three special designed mechanisms including ``Mail Sending', ``Express Transmission' and ``Double Output Buffer'. With these mechanisms, we enhance the performance by eliminating the need of using interrupt and reducing unnecessary memory copies. We evaluate the impact to the communication overhead for different size of data transmission. The results show that the ``send' operation in our protocol only takes a small constant time. The ``receive' operation also outperforms to traditional IPC and the gap will increase according to the size of data transmission. We also evaluate the ICPC performance by simulating a real world application, H.264 encoding. When comparing to traditional IPC, the results show that we get about 40\% improvements in performance. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:51:18Z (GMT). No. of bitstreams: 1 ntu-97-R95922068-1.pdf: 586928 bytes, checksum: 171736bcf3eb8e7dd6f94bb4576ee301 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | List of Tables.......................................viii
List of Figures.......................................x List of Algorithms....................................xi Chapter 1 Introduction.................................1 1.1 Motivation....................................1 1.2 Objective and Contribution..........................4 1.3 Organization...................................5 Chapter 2 Background and Formal Model.....................7 2.1 Multi-Core System-On-Chip Platform....................7 2.2 Operating System on Multi-Core Platform..................8 2.3 Monolithic Kernel vs.Micro Kernel......................10 2.4 RelatedWork..................................13 2.5 Problem Definition...............................15 2.5.1 Target Application...........................17 2.5.2 Platform Assumption.........................17 2.5.3 Inter-Core Process Communication (ICPC) protocol........18 Chapter 3 System Architecture............................19 3.1 Hardware Platform...............................19 3.1.1 ARM Subsystem............................21 3.1.2 DSP Subsystem.............................23 3.2 Operating System................................25 3.2.1 Operating System on ARM Core - OKL4..............25 3.2.2 Operating System on DSP Core - DSP/BIOS............26 Chapter 4 Inter-Core Process Communication Protocol Design.........28 4.1 Communication in Multimedia Applications................28 4.2 Observation of Communication Overhead..................31 4.3 Inter-Cores Process Communication Protocol................31 4.4 Cache Coherency Analysis...........................40 4.5 Comparison with traditional IPC protocol..................42 Chapter 5 Implementation of ICPC Service Module...............45 5.1 ICPC service overview.............................45 5.2 The Features of the ICPC Service Module..................46 5.3 ICPC Service Module Architecture......................48 5.3.1 An Easy Porting Software Architecture...............48 5.3.2 Porting Layer..............................49 5.3.3 Main Function Layer - IO Buffer Subsystem............50 5.3.4 Main Function Layer - Mailbox Subsystem.............52 5.3.5 Protocol Layer..............................54 5.4 Applicability...................................54 5.4.1 Supported Software Environment..................54 5.4.2 Supported Hardware Environment.................55 5.5 User Scenario..................................57 Chapter 6 Performance Evaluation...........60 6.1 Experiment Introduction............................60 6.2 Experiment Result...............................63 Chapter 7 Summary..................................75 References.........................................77 | |
| dc.language.iso | en | |
| dc.subject | 移植性 | zh_TW |
| dc.subject | 核心間行程通訊 | zh_TW |
| dc.subject | 異質多核心系統 | zh_TW |
| dc.subject | 效能 | zh_TW |
| dc.subject | 協定 | zh_TW |
| dc.subject | heterogeneous multi-core system | en |
| dc.subject | portability | en |
| dc.subject | protocol | en |
| dc.subject | performance | en |
| dc.subject | inter-core process communication | en |
| dc.title | 異質多核心單晶片系統之核心間行程通訊協定 | zh_TW |
| dc.title | Inter-Core Process Communication Protocol for Heterogeneous Multi-Core SoCs | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃悅民(Yueh-Min Huang),郭大維(Tei-Wei Kuo),洪士灝(Shih-Hao Hung) | |
| dc.subject.keyword | 核心間行程通訊,異質多核心系統,效能,協定,移植性, | zh_TW |
| dc.subject.keyword | inter-core process communication,heterogeneous multi-core system,performance,protocol,portability, | en |
| dc.relation.page | 78 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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