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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42143Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 洪士灝(Shih-Hao Hung) | |
| dc.contributor.author | Cheng-Yu Tsai | en |
| dc.contributor.author | 蔡承祐 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:49:07Z | - |
| dc.date.available | 2010-09-02 | |
| dc.date.copyright | 2008-09-02 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-20 | |
| dc.identifier.citation | [1] Flautner, K., Nam Sung, K., Martin, S., Blaauw, D., and Mudge, T., 'Drowsy Caches: Simple Techniques for Reducing Leakage Power',‘Book Drowsy Caches: Simple Techniques for Reducing Leakage Power’ (2002, edn.), pp. 148-157.
[2] Banakar, R., Steinke, S., Bo-Sik, L., Balakrishnan, M., and Marwedel, P., 'Scratchpad Memory: A Design Alternative for Cache on-Chip Memory in Embedded Systems',‘Book Scratchpad Memory: A Design Alternative for Cache on-Chip Memory in Embedded Systems’ (2002, edn.), pp. 73-78. [3] Verma, M., Wehmeyer, L., and Marwedel, P., 'Dynamic Overlay of Scratchpad Memory for Energy Minimization', in Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004, 2004 [4] Yi-Ping, Y., Chingren, L., and Jenq Kuen, L., 'Compilers for Leakage Power Reduction', ACM Trans. Des. Autom. Electron. Syst., vol. 11, no. 1, 2006. [5] Nguyen, N., Dominguez, A., and Barua, R., 'Scratch-Pad Memory Allocation without Compiler Support for Java Applications', in Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, 2007 [6] Angiolini, F., Menichelli, F., Ferrero, A., Benini, L., and Olivieri, M., 'A Post-Compiler Approach to Scratchpad Mapping of Code', in Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, 2004 [7] Avissar, O., Barua, R., and Stewart, D., 'An Optimal Memory Allocation Scheme for Scratch-Pad-Based Embedded Systems', Trans. on Embedded Computing Sys., vol. 1, no. 1, 2002. [8] ARM. http:///www.arm.com [9] Chiou, D., Jain, P., Rudolph, L., and Devadas, S., 'Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches', in Proceedings of the 37th conference on Design automation, 2000 [10] Egger, B., Kim, C., Jang, C., Nam, Y., Lee, J., and Min, S.L., 'A Dynamic Code Placement Technique for Scratchpad Memory Using Postpass Optimization', in Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, 2006 [11] Park, C., Lim, J., Kwon, K., Lee, J., and Min, S.L., 'Compiler-Assisted Demand Paging for Embedded Systems with Flash Memory', in Proceedings of the 4th ACM international conference on Embedded software, 2004 [12] Verma, M., and Marwedel, P., 'Overlay Techniques for Scratchpad Memories in Low Power Embedded Processors', Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, no. 8, 2006. [13] Andhi, J., Sri, P., and Ignjatovic, A., 'Hardware/Software Managed Scratchpad Memory for Embedded System', ‘Book Hardware/Software Managed Scratchpad Memory for Embedded System’ (2004, edn.), pp. 370-377. [14] Jose, B., Bruce, R.C., Jack, W.D., Jason, D.H., and Jonathan, M., 'Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Scratchpad', in Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, 2007 [15] Francesco, P., Marchal, P., Atienza, D., Benini, L., Catthoor, F., and Mendias, J.M., 'An Integrated Hardware/Software Approach for Run-Time Scratchpad Management', dac, vol. 00, 2004. [16] IBM CELL. http://www.research.ibm.com/cell/ [17] Ohara, M., Inoue, H., Sohda, Y., Komatsu, H., and Nakatani, T., 'Mpi Microtask for Programming the Cell Broadband Engine Tm Processor', IBM Syst. J., vol. 45, no. 1, 2006. [18] Mibench. http://www.eecs.umich.edu/mibench/ [19] Austin, T., Larson, E., and Ernst, D., 'Simplescalar: An Infrastructure for Computer System Modeling', Computer, vol. 35, no. 2, 2002. [20] SimpleScalar LLC. http://www.simplescalar.com/ [21] 'Frequent Loop Detection Using Efficient Nonintrusive on-Chip Hardware', IEEE Trans. Comput., vol. 54, no. 10, 2005. [22] Vivy, S., Chandrashekar, R., and Tulika, M., 'Integrated Scratchpad Memory Optimization and Task Scheduling for Mpsoc Architectures', in Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, 2006 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42143 | - |
| dc.description.abstract | 在現今的嵌入式硬體架構下，為了節省資源的消耗，往往使用草稿記憶體代替架構較為複雜的快取記憶體。然而，如何使軟體能有效率地運用草稿記憶體，已達到最佳的效能，則是一個重要的問題。我們討論了目前對於草稿記憶體的相關應用與研究，了解並且分析它們相關的優缺點後，作為我們研究方向的指標。我們提出了一個結合軟硬體的支援來達成此記憶體的效能最佳化，利用軟體的方式達成動態使用草稿記憶體的目標，並加入硬體補助的方式，來避免純軟體方式所需要導入的額外執行時間及對應的程式修改。 | zh_TW |
| dc.description.abstract | In Today's embedded system design architecture, in order to reduce resources consumption, hardware designers sometimes choose Scratchpad Memory instead of Cache. However, the management of the Scratchpad Memory by software is an important issue to get the best memory utilization. We discuss the related techniques on improving Scratchpad Memory usage, and propose an optimization mechanism which dynamically allocates the space in the scratchpad memory required by the application program. We also introduce a hardware assist to reduce the extra overhead needed by pure a software approach. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:49:07Z (GMT). No. of bitstreams: 1 ntu-97-R95922090-1.pdf: 637376 bytes, checksum: df800830a580bb2da92f6d775e52373c (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii Abstract iii 目錄 iv 圖目錄 vi 表目錄 viii 第1章 序論 1 1.1 研究動機 2 1.2 論文架構 3 第2章 相關研究與實務 4 2.1 研究分類 4 2.2 靜態配置 4 2.3 動態配置 6 2.3.1 Software Overlay 6 2.3.2 Binary/Source level Instrumentation/Modification 7 2.3.3 硬體輔助 9 2.4 討論 11 第3章 動態草稿記憶體之機制設計 12 3.1 動態記憶體轉換單元之設計 13 3.2.1 TLB對SPM的支援 14 3.2.2 e-TLB對SPM的支援 15 3.2 Interrupt Service Routine之設計 16 3.3.1 對應於TLB的ISR 17 3.3.2 對應於e-TLB的e-ISR 19 3.3 相關實作討論 21 3.3.1 Subblock實作成本 22 3.3.2 TLB實作成本 22 3.3.3 ISR實作成本 22 3.3.4 DMA實作討論 23 第4章 效能評估 24 4.1 模擬實驗環境之建造 24 4.2 實驗設計 24 4.3 實驗結果及分析 25 4.3.1 TLB機制以及Cache機制的效能 26 4.3.2 ISR Overhead 27 4.3.3 測試程式的記憶體空間需求分析 28 4.3.4 測試程式的存取分析 29 4.3.5 e-TLB機制的效能 30 4.3.6 DMA應輔助機制效能 32 第5章 結論與未來展望 34 參考文獻 35 | |
| dc.language.iso | zh-TW | |
| dc.subject | 嵌入式系統 | zh_TW |
| dc.subject | 快取 | zh_TW |
| dc.subject | 硬體設計 | zh_TW |
| dc.subject | 最佳化 | zh_TW |
| dc.subject | 效能評估 | zh_TW |
| dc.subject | 草稿記憶體 | zh_TW |
| dc.subject | performance evaluation | en |
| dc.subject | embedded system | en |
| dc.subject | Scratchpad Memory | en |
| dc.subject | optimization | en |
| dc.subject | hardware design | en |
| dc.subject | Cache | en |
| dc.title | 草稿記憶體使用率動態最佳化之軟硬體整合設計 | zh_TW |
| dc.title | Optimization of Dynamic Scratchpad Memory Utilization : A Hardware/Software Approach | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭大維(Tei-Wei Kuo),施吉昇(Chi-Sheng Shih),林 風(Phone Lin) | |
| dc.subject.keyword | 草稿記憶體,嵌入式系統,效能評估,最佳化,硬體設計,快取, | zh_TW |
| dc.subject.keyword | Scratchpad Memory,embedded system,performance evaluation,optimization,hardware design,Cache, | en |
| dc.relation.page | 37 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| Appears in Collections: | 資訊工程學系 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-97-1.pdf Restricted Access | 622.44 kB | Adobe PDF |
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